ATTINY88-MU Atmel, ATTINY88-MU Datasheet - Page 135
![MCU AVR 8K ISP FLASH 1.8V 32-QFN](/photos/12/13/121310/attiny88-mu_sml.jpg)
ATTINY88-MU
Manufacturer Part Number
ATTINY88-MU
Description
MCU AVR 8K ISP FLASH 1.8V 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32QFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Cpu Family
ATtiny
Device Core Size
8b
Frequency (max)
12MHz
Total Internal Ram Size
512Byte
# I/os (max)
28
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL
Quantity:
21 342
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY88-MUR
Manufacturer:
AT
Quantity:
20 000
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15.6
15.6.1
15.6.2
8008G–AVR–04/11
Overview of the TWI Module
SCL and SDA Pins
Bit Rate Generator Unit
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AVR data bus.
Figure 15-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
When operating in a Master mode this unit controls the period of SCL. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on bit rate or prescaler settings, but the
clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that
slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
State Machine and
Control Unit
Status control
Bit Rate Generator
Figure
Control Register
Bit Rate Register
ATtiny48/88
(TWCR)
Prescaler
(TWBR)
15-9. All registers
135
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