PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 310
![IC PIC MCU FLASH 2KX14 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F72-I/ML
Manufacturer Part Number
PIC16F72-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
6.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16F72-I/MLR
PIC16F72-I/MLR
PIC16F72-I/MLR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F72-ISO PDF datasheet #4
- PIC16F72-ISO PDF datasheet #5
- PIC16F72-ISO PDF datasheet #6
- Current page: 310 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.10
DS31017A-page 17-34
I
2
C Master Mode Repeated Start Condition Timing
A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and
the I
When the SCL pin is sampled low, the baud rate generator is loaded with the contents of
SSPADD<5:0>, and begins counting. The SDA pin is released (brought high) for one baud rate
generator count (T
SCL pin will be de-asserted (brought high). When SCL is sampled high the baud rate generator
is re-loaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be
sampled high for one T
for one T
cally cleared, and the baud rate generator is not reloaded, leaving the SDA pin held low. As soon
as a start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set.
The SSPIF bit will not be set until the baud rate generator has timed-out.
Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit
address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are
transmitted and an ACK is received, the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
Note 1: If RSEN is programmed while any other event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start condition occurs if:
2
C logic module is in the idle state. When the RSEN bit is set, the SCL pin is asserted low.
BRG
• SDA is sampled low when SCL goes from low to high.
• SCL goes low before SDA is asserted low. This may indicates that another
while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automati-
master is attempting to transmit a data ‘1’.
BRG
). When the baud rate generator times out, if SDA is sampled high, the
BRG
. This action is then followed by assertion of the SDA pin (SDA = 0)
Preliminary
1997 Microchip Technology Inc.
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