PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 683

• Manufacturer Part Number: PIC16F72-I/ML
• Description: IC PIC MCU FLASH 2KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F72-I/MLR; PIC16F72-I/MLR

Glossary
S
Sampling Time
Sampling time is the complete time to get an A/D result. It includes the acquisition time and the
conversion time.
Serial Peripheral Interface (SPI)
This is one of the modes of the SSP module. This is typically a 3-wire interface, with a data out
line, a data in line, and a clock line. Since the clock is present, this is a synchronous interface.
SFR
Special Function Register. These registers contain the control bits and status information for the
device.
Single cycle instruction
An instruction that executes in a “single” machine cycle (T
).
CY
Sleep
This is the low power mode of the device, where the device’s oscillator is disabled.This reduces
the current the device consumes. Certain peripherals may be placed into modes where they con-
tinue to operate.
Special Function Registers (SFR)
These registers contain the control bits and status information for the device.
SPI
See Serial Peripheral Interface.
Stack
A portion of the CPU which retains the return address for program execution. The stack gets
loaded with the value in the Program Counter when a
CALL
instruction is executed or an interrupt
occurs.
35
1997 Microchip Technology Inc.
DS31035A-page 35-11