AT90PWM216-16SU Atmel, AT90PWM216-16SU Datasheet - Page 160
AT90PWM216-16SU
Manufacturer Part Number
AT90PWM216-16SU
Description
MCU AVR 16K ISP FLSH 16MHZ24SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM216-16SU.pdf
(359 pages)
Specifications of AT90PWM216-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.21 Interrupt Handling
16.22 PSC Synchronization
160
AT90PWM216/316
This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-
tion of the ADC. It this case, it’s minimum value is 1.
As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector
...)
List of interrupt sources:
2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible:
Figure 16-38. PSC Run Synchronization
If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1.
• Counter reload (end of On Time 1)
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
• The waveforms are center aligned in the Center Aligned mode if master and slaves are all
• The waveforms are edge aligned in the 1, 2 or 4 ramp mode
with the same PSC period (which is the natural use).
PRUN0
PARUN0
PRUN1
PARUN1
PRUN2
PARUN2
SY0In
SY1In
SY2In
SY0Out
SY1Out
SY2Out
Run PSC0
Run PSC1
Run PSC2
PSC0
PSC1
PSC2
7710E–AVR–08/10
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