PIC18F2221-I/SP Microchip Technology, PIC18F2221-I/SP Datasheet - Page 385
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PIC18F2221-I/SP
Manufacturer Part Number
PIC18F2221-I/SP
Description
IC PIC MCU FLASH 2KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18F2221-I/SP
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2221-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Data Memory ..................................................................... 59
DAW ................................................................................. 292
DC and AC Characteristics
DC Characteristics ........................................................... 340
DCFSNZ .......................................................................... 293
DECF ............................................................................... 292
DECFSZ ........................................................................... 293
Dedicated ICD/ICSP Port ................................................. 271
Development Support ...................................................... 323
Device Differences ........................................................... 377
Device Overview .................................................................. 7
Device Reset Timers .......................................................... 45
Direct Addressing ............................................................... 68
E
Effect on Standard PIC Instructions ................................. 320
Effects of Power-Managed Modes on
Electrical Characteristics .................................................. 327
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
© 2007 Microchip Technology Inc.
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 69
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18F4321 Family ...................................... 60
Special Function Registers ........................................ 62
Graphs and Tables .................................................. 365
Power-Down and Supply Current ............................ 331
Supply Voltage ......................................................... 330
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Various Clock Sources ............................................... 32
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 232
A/D Minimum Charging Time ................................... 232
Asynchronous Mode ................................................ 215
Baud Rate Generator
12-Bit Break Transmit and Receive ................. 221
Associated Registers, Receive ........................ 219
Associated Registers, Transmit ....................... 217
Auto-Wake-up on Sync Break ......................... 220
Receiver ........................................................... 218
Setting up 9-Bit Mode with
Transmitter ....................................................... 215
Operation in Power-Managed Mode ................ 209
Address Detect ........................................ 218
Preliminary
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 253, 266
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 273
Flash Program Memory ..................................................... 73
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 294
PIC18F4321 FAMILY
Baud Rate Generator (BRG) ................................... 209
Synchronous Master Mode ...................................... 222
Synchronous Slave Mode ........................................ 225
ADDFSR .................................................................. 316
ADDULNK ............................................................... 316
and Using MPLAB IDE Tools .................................. 322
CALLW .................................................................... 317
Considerations for Use ............................................ 320
MOVSF .................................................................... 317
MOVSS .................................................................... 318
PUSHL ..................................................................... 318
SUBFSR .................................................................. 319
SUBULNK ................................................................ 319
Syntax ...................................................................... 315
Exiting Operation ..................................................... 266
Interrupts in Power-Managed Modes ...................... 267
POR or Wake from Sleep ........................................ 267
WDT During Oscillator Failure ................................. 266
Associated Registers ................................................. 81
Control Registers ....................................................... 74
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing ....................................................................... 79
Associated Registers ....................................... 210
Auto-Baud Rate Detect .................................... 213
Baud Rate Error, Calculating ........................... 210
Baud Rates, Asynchronous Modes ................. 211
High Baud Rate Select (BRGH Bit) ................. 209
Sampling ......................................................... 209
Associated Registers, Receive ........................ 224
Associated Registers, Transmit ....................... 223
Reception ........................................................ 224
Transmission ................................................... 222
Associated Registers, Receive ........................ 226
Associated Registers, Transmit ....................... 225
Reception ........................................................ 226
Transmission ................................................... 225
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Boundaries ........................................................ 76
Boundaries Based on Operation ....................... 76
Operations with TBLRD and TBLWT (table) ..... 76
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
DS39689E-page 383