PIC18F2221-I/SP Microchip Technology, PIC18F2221-I/SP Datasheet - Page 46
![IC PIC MCU FLASH 2KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2221-I/SP
Manufacturer Part Number
PIC18F2221-I/SP
Description
IC PIC MCU FLASH 2KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18F2221-I/SP
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2221-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2321-IML PDF datasheet #5
- Current page: 46 of 396
- Download datasheet (7Mb)
PIC18F4321 FAMILY
4.4
PIC18F4321 family devices implement a BOR circuit
that provides the user with a number of configuration
and power-saving options. The BOR is controlled by
the BORV1:BORV0 and BOREN1:BOREN0 Configu-
ration bits. There are a total of four BOR configurations
which are summarized in Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0,
except ‘00’), any drop of V
D005) for greater than T
the device. A Reset may or may not occur if V
below V
Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.
BOR
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
4.4.1
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
TABLE 4-1:
DS39689E-page 44
DD
BOREN1
BOR Configuration
rises above V
0
0
1
1
and
BOR
for
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
for less than T
an
the
BOREN0
BOR CONFIGURATIONS
DD
additional
BOR
Power-on
0
1
0
1
DD
rises above V
; it then will keep the chip in
DD
drops below V
BOR
BOR
rises above V
DD
(RCON<6>)
Unavailable
Unavailable
Unavailable
(parameter 35) will reset
SBOREN
Available
below V
Status of
. The chip will remain in
time
Timer
BOR
delay,
BOR
, the Power-up
BOR
(PWRT)
BOR
(parameter
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
.
while the
DD
T
PWRT
falls
Preliminary
are
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi-
nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4.2
When Brown-out Reset is enabled, the BOR bit always
resets to ‘0’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If BOR is
‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
4.4.3
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software control,
the Brown-out Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
© 2007 Microchip Technology Inc.
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