AT90PWM3-16MQ Atmel, AT90PWM3-16MQ Datasheet - Page 253

• Manufacturer Part Number: AT90PWM3-16MQ
• Description: IC AVR MCU FLASH 8K 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16MQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4317J–AVR–08/10
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In case the amplifier output is modified during the sample phase of the ADC, the on-
going conversion is aborted and restarted as soon as the output of the amplifier is stable. This
ensure a fast response time. The only precaution to take is to be sure that the trig signal (PSC)
frequency is lower than ADCclk/4.
Figure 21-16. Amplifier synchronization timing diagram for AT90PWM2B/3B
Figure 21-17. Amplifier synchronization timing diagram for AT90PWM2B/3B
Block
ADC
PSC
(Sync Clock)
Si g nal to be
PS Cn_ASY
AMPLI_clk
measu red
CK ADC
Activity
ADSC
ADC
With change on analog input signal
ADSC is set when the amplifier output is changing due to the amplifier clock
switch.
Sampling
ADC
Conv
ADC
ADC Result
Delta V
Ready
AT90PWM2/3/2B/3B
4th stable sample
Sampling
ADC
Valid sample
Conv
ADC
ADC Result
Ready
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