PIC18F4221-I/P Microchip Technology, PIC18F4221-I/P Datasheet - Page 358

• Manufacturer Part Number: PIC18F4221-I/P
• Description: IC PIC MCU FLASH 2KX16 400IP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4221-I/P

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F4321 FAMILY
FIGURE 26-15:
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
DS39689E-page 356
70
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
83
Note 1:
Param
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SCK
SDO
SS
SCK
2:
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ SS ↑ to SDO Output High-Impedance
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
Symbol
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Refer to Figure 26-5 for load conditions.
SCK Input High Time
SCK Input Low Time
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time (Master mode) PIC18FXXXX
SCK Output Fall Time (Master mode)
SS ↓ to SCK ↓ or SCK ↑ Input
(Slave mode)
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Valid after SCK Edge PIC18FXXXX
SS ↑ after SCK edge
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
70
80
71
73
MSb In
MSb
Characteristic
74
72
75, 76
Preliminary
bit 6 - - - - - -1
bit 6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
PIC18FXXXX
PIC18LFXXXX
PIC18LFXXXX
PIC18LFXXXX
78
79
1.25 T
1.25 T
1.5 T
79
78
LSb In
Min
T
100
100
LSb
CY
CY
40
40
—
10
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2007 Microchip Technology Inc.
77
Max Units Conditions
100
25
45
25
50
25
45
25
50
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
V
V
V
DD
DD
DD
= 2.0V
= 2.0V
= 2.0V