PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet
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... PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers 2004 Microchip Technology Inc. Data Sheet with nanoWatt Technology Preliminary DS39635A ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8310 8K/2M 4096/1M PIC18F8410 16K/2M 8192/1M 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Four external interrupts • Four input change interrupts • Four 8-bit/16-bit Timer/Counter modules • Capture/Compare/PWM (CCP) modules • Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ ...
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... RE0/RD 2 RG0/CCP3 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing DS39635A-page PIC18F6310 PIC18F6410 Preliminary 50 49 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 33 ...
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... RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 Note 1: RE7 is the alternate pin for CCP2 multiplexing 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F8310 PIC18F8410 Preliminary RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 56 (1) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI/RA7 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 387 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 387 Index .................................................................................................................................................................................................. 389 On-Line Support................................................................................................................................................................................. 399 Systems Information and Upgrade Hot Line ...................................................................................................................................... 399 Reader Response .............................................................................................................................................................................. 400 PIC18F6310/6410/8310/8410 Product Identification System ............................................................................................................ 401 DS39635A-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 5 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6310/6410/8310/8410 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F6310/6410/8310/8410 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... Like all Microchip PIC18 devices, members of the PIC18F6310/6410/8310/8410 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an “F” in the part number (such as PIC18F6310), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF6410), ...
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... Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, RESET Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F6310 PIC18F6410 DC – 40 MHz DC – 40 MHz 8K 16K 4096 8192 768 768 ...
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... PIC18F6310/6410/8310/8410 FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (48/64 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode and Control (3) Internal ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Latch 8 8 Data Memory ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR RG5 MCLR V PP OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/HLVDIN 27 RA5 AN4 HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 48 RB0 INT0 RB1/INT1 47 RB1 INT1 RB2/INT2 46 RB2 INT2 RB3/INT3 45 RB3 INT3 RB4/KBI0 44 RB4 KBI0 RB5/KBI1 43 RB5 KBI1 RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 KBI3 PGD Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 29 RC1 T1OSI (1) CCP2 RC2/CCP1 33 RC2 CCP1 RC3/SCK/SCL 34 RC3 SCK SCL RC4/SDI/SDA 35 RC4 SDI SDA RC5/SDO 36 RC5 SDO RC6/TX1/CK1 31 RC6 TX1 CK1 RC7/RX1/DT1 32 RC7 RX1 ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/PSP0 58 RD0 PSP0 RD1/PSP1 55 RD1 PSP1 RD2/PSP2 54 RD2 PSP2 RD3/PSP3 53 RD3 PSP3 RD4/PSP4 52 RD4 PSP4 RD5/PSP5 51 RD5 PSP5 RD6/PSP6 50 RD6 PSP6 RD7/PSP7 49 RD7 PSP7 Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD 2 RE0 RD RE1/WR 1 RE1 WR RE2/CS 64 RE2 CS RE3 63 RE4 62 RE5 61 RE6 60 RE7/CCP2 59 RE7 (2) CCP2 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 18 RF0 AN5 RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 RF2 AN7 C1OUT RF3/AN8 15 RF3 AN8 RF4/AN9 14 RF4 AN9 RF5/AN10/CV 13 REF RF5 AN10 CV REF RF6/AN11 12 RF6 AN11 RF7/SS 11 RF7 SS Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/CCP3 3 RG0 CCP3 RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3 6 RG4 8 RG5 V 9, 25, 41 10, 26, 38 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR RG5 MCLR V PP OSC1/CLKI/RA7 49 OSC1 CLKI RA7 OSC2/CLKO/RA6 50 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode) ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 58 RB0 INT0 RB1/INT1 57 RB1 INT1 RB2/INT2 56 RB2 INT2 RB3/INT3/CCP2 55 RB3 INT3 (1) CCP2 RB4/KBI0 54 RB4 KBI0 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 KBI3 PGD Legend: TTL = TTL compatible input ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/AD0/PSP0 72 RD0 AD0 PSP0 RD1/AD1/PSP1 69 RD1 AD1 PSP1 RD2/AD2/PSP2 68 RD2 AD2 PSP2 RD3/AD3/PSP3 67 RD3 AD3 PSP3 RD4/AD4/PSP4 66 RD4 AD4 PSP4 RD5/AD5/PSP5 65 RD5 AD5 PSP5 RD6/AD6/PSP6 64 RD6 AD6 PSP6 ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 24 RF0 AN5 RF1/AN6/C2OUT 23 RF1 AN6 C2OUT RF2/AN7/C1OUT 18 RF2 AN7 C1OUT RF3/AN8 17 RF3 AN8 RF4/AN9 16 RF4 AN9 RF5/AN10/CV 15 REF RF5 AN10 CV REF RF6/AN11 14 RF6 AN11 RF7/SS 13 RF7 SS Legend: TTL = TTL compatible input ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RJ0/ALE 62 RJ0 ALE RJ1/OE 61 RJ1 OE RJ2/WRL 60 RJ2 WRL RJ3/WRH 59 RJ3 WRH RJ4/BA0 39 RJ4 BA0 RJ5/CE 40 RJ4 CE RJ6/LB 41 RJ6 LB RJ7/UB 42 RJ7 UB V 11, 31, 51 12, 32, 48 Legend: TTL = TTL compatible input ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F6310/6410/8310/8410 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F6310/6410/8310/8410 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... EXT C > EXT 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F6310/6410/8310/8410 2.6 Internal Oscillator Block The PIC18F6310/6410/8310/8410 devices include an internal oscillator block, which generates two different clock signals; either can be used as the microcontrol- ler’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Minimum frequency Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.6.5.3 Compensating with the Timers A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F6310/6410/8310/8410 devices are shown in Figure 2-8. See Section 23.0 “Special Features of the CPU” for configuration register details ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS PIC18F6310/6410/8310/8410 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F6310/6410/8310/8410 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 IDLEN IRCF2 bit 7 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 38 Preliminary 2004 Microchip Technology Inc. ...
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... POWER MANAGED MODES PIC18F6310/6410/8310/8410 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power managed modes: • Sleep mode • ...
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... PIC18F6310/6410/8310/8410 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 OST OSC PLL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 n-1 n Clock Transition OST (1) PLL ( n-1 Clock Transition ...
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... PIC18F6310/6410/8310/8410 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code ...
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... The Power Managed Sleep mode PIC18F6310/6410/8310/8410 devices is identical to the Legacy Sleep mode offered in all other PICmicro devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (see Figure 3-5). All clock source status bits are cleared ...
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... PIC18F6310/6410/8310/8410 3.4.1 PRI_IDLE MODE This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled, but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer ...
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... PIC18F6310/6410/8310/8410 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Section 3.2 “ ...
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... Includes both the INTOSC 8 MHz source and postscaler derived frequencies the Oscillator Start-up Timer (parameter 32). t OST also designated PLL 5: Execution continues during T 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Clock Source Exit Delay after Wake-up LP, XT, HS HSPLL T CSD (1) EC, RC, INTRC (3) INTOSC ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 48 Preliminary 2004 Microchip Technology Inc. ...
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... RESET The PIC18F6310/6410/8310/8410 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F6310/6410/8310/8410 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 IPEN SBOREN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN1:BOREN0 = 01 BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00 11: Bit is disabled and read as ‘ ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F6310/6410/8310/8410 devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.7 “PORTG, TRISG and LATG Registers” ...
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... PIC18F6310/6410/8310/8410 4.4 Brown-out Reset (BOR) PIC18F6310/6410/8310/8410 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 configuration bits. There are a total of four BOR configurations, which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If ...
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... POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) PIC18F6310/6410/8310/8410 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 µs = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation ...
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... PIC18F6310/6410/8310/8410 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 , V RISE > PWRT T OST T PWRT T OST ...
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... PIC18F6310/6410/8310/8410 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F6310/6410/8310/8410 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices INDF2 6X10 8X10 POSTINC2 6X10 8X10 POSTDEC2 6X10 8X10 PREINC2 6X10 8X10 PLUSW2 6X10 8X10 FSR2H 6X10 8X10 FSR2L 6X10 8X10 STATUS 6X10 8X10 TMR0H 6X10 8X10 TMR0L 6X10 8X10 ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F6310/6410/8310/8410 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices TRISG 6X10 8X10 TRISF 6X10 8X10 TRISE 6X10 8X10 TRISD 6X10 8X10 TRISC 6X10 8X10 TRISB 6X10 8X10 (5) TRISA 6X10 8X10 LATJ 6X10 8X10 LATH 6X10 8X10 LATG 6X10 8X10 ...
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... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Program Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F6310/6410/8310/8410 DEVICES PIC18FX310 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 • ...
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... Flash memory. Attempts to read above the physical limit of the on-chip Flash (3FFFh) causes a read of all ‘0’s (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6310 and PIC18F6410 devices. REGISTER 5-1: CONFIG3L: CONFIGURATION BYTE REGISTER 3 LOW R/P-1 R/P-1 ...
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... Mode From Microcontroller Yes Extended Yes Microcontroller Microprocessor No Access No Access Microprocessor Yes w/ Boot Block 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Extended Microcontroller Mode 000000h (Top of Memory) (Top of Memory 1FFFFFh Microprocessor with Boot Block Mode 000000h 0007FFh 000800h (No (Top of Memory 1FFFFFh Flash ...
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... PIC18F6310/6410/8310/8410 5.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software, or until a POR occurs ...
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... PIC18F6310/6410/8310/8410 5.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F6310/6410/8310/8410 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
Page 71
... PIC18F6310/6410/8310/8410 devices implement only 3 complete banks, for a total of 768 bytes. Figure 5-6 shows the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’ ...
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... PIC18F6310/6410/8310/8410 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F6310/6410/8310/8410 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh DS39635A-page 70 Data Memory Map 000h Access RAM 05Fh 060h ...
Page 73
... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Memory 000h 7 00h Bank 0 ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 5-2 and Table 5-3. TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6310/6410/8310/8410 DEVICES Address Name Address FFFh ...
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... TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) (6) (6) STKPTR STKFUL STKUNF — PCLATU — — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
Page 76
... PIC18F6310/6410/8310/8410 TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON IPEN SBOREN — ...
Page 77
... TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRG1 EUSART1 Baud Rate Generator RCREG1 EUSART1 Receive Register TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN IPR3 — — RC2IP PIR3 — — RC2IF PIE3 — ...
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... PIC18F6310/6410/8310/8410 TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH1 EUSART1 Baud Rate Generator High Byte BAUDCON1 ABDOVF RCIDL — SPBRG2 AUSART2 Baud Rate Generator RCREG2 AUSART2 Receive Register TXREG2 AUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN ...
Page 79
... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the bits in the Status register. ...
Page 80
... PIC18F6310/6410/8310/8410 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 81
... FCCh will be added to that of the W register and stored back in FCCh. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... PIC18F6310/6410/8310/8410 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: • ...
Page 83
... This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
Page 84
... PIC18F6310/6410/8310/8410 FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
Page 85
... BSR. F60h FFFh 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. Any indirect or ...
Page 86
... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 84 Preliminary 2004 Microchip Technology Inc. ...
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... If a table write is being used to write executable code into an external program memory, program instructions will need to be word-aligned. Note: Although it cannot be used in PIC18F6310 devices in normal operation, the TBLWT instruction is still implemented in the instruction set. Executing the instruction takes two instruction cycles, but effectively results in a NOP ...
Page 88
... PIC18F6310/6410/8310/8410 6.2 Control Registers Two control registers are used in conjunction with the TBLRD and TBLWT instructions: the TABLAT register and the TBLPTR register set. 6.2.1 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between the program memory space and data RAM ...
Page 89
... The best place for timing and instruction sequence requirements is the data sheet of the memory device in question. For additional information on algorithm design for the external 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ...
Page 90
... PIC18F6310/6410/8310/8410 The TBLWT operation on write blocks is somewhat different than the word write PIC18F8310/8410 devices described here. A more complete description of block write operations is provided in the Microchip document “Programming Specifications for PIC18FX410/X490 Flash MCUs” (DS39624). TABLE 6-2: REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY ...
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... Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 As implemented here, the interface is similar to that introduced on PIC18F8X20 microcontrollers. The most notable difference PIC18F8310/8410 devices supports both 16-bit and Multiplexed 8-bit Data Width modes ...
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... PIC18F6310/6410/8310/8410 TABLE 7-1: PIC18F8310/8410 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit RD0/AD0/PSP0 PORTD 0 Input/Output or System Bus Address bit 0 or Data bit 0 or Parallel Slave Port bit 0 RD1/AD1/PSP1 PORTD 1 Input/Output or System Bus Address bit 1 or Data bit 1 or Parallel Slave Port bit 1 ...
Page 93
... WRL Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 at any time that the microcontroller accesses external memory, whether reading or writing inactive (asserted high) whenever the device is in Sleep mode. ...
Page 94
... PIC18F6310/6410/8310/8410 7.2.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-bit Word Write mode for PIC18F6410 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
Page 95
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2: Demultiplexing is only required when multiple memory devices are accessed. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 96
... PIC18F6310/6410/8310/8410 7.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 through Figure 7-6. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE Apparent Q ...
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... EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE A<19:16> 00h AD<15:0> 3AAAh 0003h CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Bus Inactive DS39635A-page 95 ...
Page 98
... PIC18F6310/6410/8310/8410 7.3 8-Bit Mode The external memory interface implemented in PIC18F6410 devices operates only in Multiplexed 8-bit mode; data shares the 8 Least Significant bits of the address bus. Figure 7-1 shows an example of 8-bit Multiplexed mode for PIC18F8310/8410 devices. This mode is used for a single 8-bit memory connected for 16-bit operation ...
Page 99
... EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:8> AD<7:0> CE ALE OE Opcode Fetch Memory TBLRD * Cycle from 000100h Instruction INST(PC – 2) Execution 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 0Eh 55h 33h Table Read of 92h from 199E67h TBLRD Cycle 2 Q1 ...
Page 100
... PIC18F6310/6410/8310/8410 FIGURE 7-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:8> 3Ah AD<7:0> AAh 00h 03h CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution DS39635A-page 00h 3Ah 0Eh 55h ABh Opcode Fetch Sleep Mode, ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 102
... PIC18F6310/6410/8310/8410 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ...
Page 103
... Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices have ...
Page 104
... PIC18F6310/6410/8310/8410 FIGURE 9-1: PIC18F6310/6410/8310/8410 INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<5:4, 0> PIE3<5:4, 0> IPR3<5:4, 0> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<5:4, 0> PIE3<5:4, 0> ...
Page 105
... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
Page 106
... PIC18F6310/6410/8310/8410 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 107
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 INT3IE ...
Page 108
... PIC18F6310/6410/8310/8410 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 109
... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 U-0 R/W-0 — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 110
... PIC18F6310/6410/8310/8410 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: AUSART Receive Interrupt Flag bit 1 = The AUSART receive buffer, RCREG, is full (cleared when RCREG is read The AUSART receive buffer is empty bit 4 ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 112
... PIC18F6310/6410/8310/8410 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 OSCFIE CMIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit ...
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... Disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R-0 R-0 U-0 — RC2IE TX2IE — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 114
... PIC18F6310/6410/8310/8410 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 U-0 R/W-1 — — BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 116
... PIC18F6310/6410/8310/8410 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: AUSART Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: AUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-1 Unimplemented: Read as ‘ ...
Page 117
... For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-1 R-1 — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 118
... PIC18F6310/6410/8310/8410 9.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set ...
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... Port Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
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... PIC18F6310/6410/8310/8410 TABLE 10-1: PORTA FUNCTIONS TRIS Pin Name Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/V - RA2 REF 0 1 AN2 REF RA3/AN3/V + RA3 0 REF 1 AN3 REF RA4/T0CKI RA4 0 1 T0CKI x RA5/AN4/HLVDIN RA5 0 1 AN4 1 HLVDIN 1 OSC2 x OSC2/CLKO/RA6 CLKO ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 122
... PIC18F6310/6410/8310/8410 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 123
... Alternate assignment for CCP2 when the CCP2MX configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD operations are enabled. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATB< ...
Page 124
... PIC18F6310/6410/8310/8410 TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Data Output Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
Page 125
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 126
... PIC18F6310/6410/8310/8410 TABLE 10-5: PORTC FUNCTIONS TRIS Pin Name Function Setting RC0/T1OSO/T13CKI RC0 0 1 T1OSO x T13CKI 1 RC1/T1OSI/CCP2 RC1 0 1 T1OSI x (1) CCP2 0 1 RC2/CCP1 RC2 0 1 CCP1 0 1 RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA 1 1 RC5/SDO ...
Page 127
... Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register Legend: Shaded cells are not used by PORTC. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 Bit 0 ...
Page 128
... PIC18F6310/6410/8310/8410 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATD< ...
Page 130
... PIC18F6310/6410/8310/8410 TABLE 10-7: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RD7/AD7/PSP7 RD7 0 1 (2) AD7 x x PSP7 x x Legend: PWR = Power Supply Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
Page 131
... PORTE is the high-order byte of the multiplexed address/data bus (AD15:AD8). The TRISE bits are also overridden. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and RE2/AD10/CS) are configured as digital control inputs for the port ...
Page 132
... PIC18F6310/6410/8310/8410 TABLE 10-9: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/RD RE0 0 1 (3) AD8 RE1/AD9/WR RE1 0 1 (3) AD9 RE2/AD10/CS RE2 0 1 (3) AD10 RE3/AD11 RE3 0 1 (3) AD11 x x RE4/AD12 RE4 0 1 (3) AD12 x x RE5/AD13 RE5 0 1 (3) AD13 x x RE6/AD14 RE6 0 1 (3) AD14 ...
Page 133
... Bit 6 PORTE RE7 RE6 LATE LATE Data Output Register TRISE PORTE Data Direction bits Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 Preliminary ...
Page 134
... PIC18F6310/6410/8310/8410 10.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
Page 135
... CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATF<0> data output; not affected by analog input PORTF<0> data input; disabled when analog input enabled. ...
Page 136
... PIC18F6310/6410/8310/8410 10.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide, bidirectional port. The corre- sponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i ...
Page 137
... TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 is available as an input only when MCLR is disabled. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATG<0> data output PORTG<0> data input. ...
Page 138
... PIC18F6310/6410/8310/8410 10.8 PORTH, LATH and TRISH Registers Note: PORTH is available PIC18F8310/8410 devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 139
... TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 TRISH PORTH Data Direction Control Register PORTH Read PORTH pin/Write PORTH Data Latch LATH Read PORTH Data Latch/Write PORTH Data Latch 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATH<0> data output PORTH<0> data input. O DIG External memory interface, address line 16 ...
Page 140
... PIC18F6310/6410/8310/8410 10.9 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available PIC18F8310/8410 devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 141
... TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ Read PORTJ pin/Write PORTJ Data Latch LATJ LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output ...
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... PIC18F6310/6410/8310/8410 10.10 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: ...
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... Value at POR FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Q3 ...
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... PIC18F6310/6410/8310/8410 FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD PORTD Data Latch when written; Port pins when read LATD LATD Data Output bits TRISD PORTD Data Direction bits PORTE PORTE Data Latch when written ...
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... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
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... PIC18F6310/6410/8310/8410 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default, unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the fol- lowing two instruction cycles ...
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... T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. the prescaler 11 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 146 Preliminary 2004 Microchip Technology Inc. ...
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... Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power managed operation ...
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... PIC18F6310/6410/8310/8410 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
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... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F6310/6410/8310/8410 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
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... RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 152 Preliminary 2004 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F6310/6410/8310/8410 13.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the CCP modules (see Section 15.1.1 “ ...
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... PIC18F6310/6410/8310/8410 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous counter • Asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM ...
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... RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 158 Preliminary 2004 Microchip Technology Inc. ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6310/6410/8310/8410 devices have three CCP (Capture/Compare/PWM) modules, labelled CCP1, CCP2 and CCP3. All modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. REGISTER 15-1: CCPXCON: CCP1/CCP2/CCP3 CONTROL REGISTER U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ ...
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... PIC18F6310/6410/8310/8410 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 ...
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... Prescaler ÷ Q1:Q4 CCP3CON<3:0> CCP3 pin Prescaler ÷ 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 15.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: If RC1/CCP2 or RE7/CCP2 is configured as an output, a write to the port can cause a capture condition ...
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... PIC18F6310/6410/8310/8410 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP2IE (PIE2<1>) clear to avoid false interrupts and should clear the flag bit, CCP2IF, following any such change in operating mode. 15.2.4 CCP PRESCALER There are four prescaler settings in Capture mode ...
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... FIGURE 15-3: COMPARE MODE OPERATION BLOCK DIAGRAM T3CCP2 0 1 T3CCP1 TMR1H TMR1L 0 TMR3H TMR3L 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Special Event Trigger (Timer1/Timer3 Reset) Set CCP1IF Output Compare Comparator Match Logic 4 CCPR1H CCPR1L CCP1CON<3:0> Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) ...
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... PIC18F6310/6410/8310/8410 TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN SBOREN PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP PIR3 — ...
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... Q clock bits of the prescaler, to create the 10-bit time base. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A PWM output (Figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 168
... PIC18F6310/6410/8310/8410 15.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>. The following equation is ...
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... CCPR3L Capture/Compare/PWM Register 3 (LSB) CCPR3H Capture/Compare/PWM Register3 (MSB) CCP3CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — RC1IF ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 168 Preliminary 2004 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 172
... PIC18F6310/6410/8310/8410 16.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC /16 OSC ...
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... PIC18F6310/6410/8310/8410 16.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 175
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3.4 TYPICAL CONNECTION Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... PIC18F6310/6410/8310/8410 16.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 16- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
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... Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...
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... PIC18F6310/6410/8310/8410 FIGURE 16-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 16-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 16.3.10 BUS MODE COMPATIBILITY ...
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... PIC18F6310/6410/8310/8410 2 16 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing ...
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... Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C MODE) R-0 R-0 R-0 (1) ...
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... PIC18F6310/6410/8310/8410 REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I a transmission to be started (must be cleared in software collision In Slave Transmit mode: ...
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... Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C MODE) R/W-0 R/W-0 R/W-0 (1) (2) ...
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... PIC18F6310/6410/8310/8410 16.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I operation. Four mode selection bits (SSPCON<3:0>) 2 allow one of the following I C modes to be selected: 2 • Master mode, clock = (F /4) x (SSPADD + 1) ...
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... The clock must be released by setting bit CKP (SSPCON<4>). See Section 16.4.4 “Clock Stretching” for more detail. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39635A-page 184 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 185 ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 16-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39635A-page 186 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 187 ...
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... PIC18F6310/6410/8310/8410 16.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... DX SCL CKP WR SSPCON 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12) ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39635A-page 190 Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 16-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 191 ...
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... PIC18F6310/6410/8310/8410 16.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all ...
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... FIGURE 16-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condi- tion is complete ...
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... PIC18F6310/6410/8310/8410 2 16.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... PIC18F6310/6410/8310/8410 16.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the ...
Page 199
... FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: If, at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the SCL line is sampled low before the SDA ...
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... PIC18F6310/6410/8310/8410 2 16.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sam- pled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...