DSPIC30F3012-30I/SO Microchip Technology, DSPIC30F3012-30I/SO Datasheet - Page 136

• Manufacturer Part Number: DSPIC30F3012-30I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 18SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301230ISO

TABLE 17-7:
TABLE 17-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
2:
3:
1:
2:
3:
Address
0740
0742
0744
0770
0772
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Reset state depends on type of reset.
Reset state depends on Configuration bits.
Only available on dsPIC30F3013 devices.
— = unimplemented bit, read as ‘0’
These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
Reserved bits read as ‘1’ and must be programmed as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
TRAPR
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
Bit 15
—
—
—
—
FWDTEN
MCLREN
BKBUG
Bit 15
FCKSM<1:0>
—
—
—
IOPUWR
Bit 14
—
—
—
Bit 14
COSC<2:0>
COE
—
—
—
—
—
Bit 13
BGST LVDEN
T3MD
—
—
Bit 13
—
—
—
—
—
Bit 12
T2MD
Reserved
Reserved
—
—
Bit 12
Bit 11
T1MD
(2)
(2)
—
—
—
—
—
—
—
—
Bit 10
—
—
—
LVDL<3:0>
Bit 11
—
—
—
—
—
—
—
NOSC<2:0>
IC2MD IC1MD
Bit 9
—
—
PWMPIN
Bit 10
—
—
—
—
—
Bit 8
—
—
(1)
FOS<2:0>
I2CMD U2MD
HPOL
EXTR
Bit 7
Bit 9
—
—
POST<1:0>
—
—
—
—
Reserved
(1)
SWR
Reserved
Bit 6
—
—
LPOL
Bit 8
(2)
(3)
—
—
—
(1)
SWDTEN
(2)
U1MD
LOCK
Bit 5
—
—
BOREN
Bit 7
—
—
—
—
—
—
WDTO
Bit 4
—
—
—
—
Bit 6
—
—
—
—
—
—
—
SPI1MD
SLEEP
TUN3
Bit 3
CF
—
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
TUN2
Bit 2
IDLE
—
—
—
Bit 4
LPOSCEN
—
—
—
—
OC2MD
TUN1
Bit 1
BOR
—
Bit 3
—
—
—
OSWEN
ADCMD
OC1MD
TUN0
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
0000 0000 0000 0000
0000 0000 0000 0000
(3)
Reset State
(Note 1)
(Note 2)
(Note 2)
(2)
(2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0