DSPIC30F3012-30I/SO Microchip Technology, DSPIC30F3012-30I/SO Datasheet - Page 88

IC DSPIC MCU/DSP 24K 18SOIC

DSPIC30F3012-30I/SO

Manufacturer Part Number
DSPIC30F3012-30I/SO
Description
IC DSPIC MCU/DSP 24K 18SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/SO

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
18SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301230ISO

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3012-30I/SO
Manufacturer:
Microchip Technology
Quantity:
1 798
Part Number:
DSPIC30F3012-30I/SO
Manufacturer:
MICRCOHI
Quantity:
20 000
dsPIC30F2011/2012/3012/3013
12.1
Each output compare channel can select between one
of two 16-bit timers, Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.
12.2
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
12.3
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is
configured for one of two Dual Output Compare modes,
which are:
• Single Output Pulse mode
• Continuous Output Pulse mode
12.3.1
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
• Determine instruction cycle time T
• Calculate desired pulse width value based on T
• Calculate time to start pulse from timer start value
• Write pulse width start and stop times into OCxR
• Set Timer Period register to value equal to or
• Set OCM<2:0> = 100.
• Enable timer, TON bit (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
DS70139G-page 88
of 0x0000.
and OCxRS Compare registers (x denotes
channel 1 to N).
greater than value in OCxRS Compare register.
Timer2 and Timer3 Selection Mode
Simple Output Compare Match
Mode
Dual Output Compare Match Mode
SINGLE PULSE MODE
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12.3.2
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
• Determine instruction cycle time T
• Calculate desired pulse value based on T
• Calculate timer to start pulse width from timer start
• Write pulse width start and stop times into OCxR
• Set Timer Period register to value equal to or
• Set OCM<2:0> = 101.
• Enable timer, TON bit (TxCON<15>) = 1.
12.4
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is
configured for the PWM mode of operation. When
configured for the PWM mode of operation, OCxR is
the main latch (read-only) and OCxRS is the secondary
latch. This enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1.
2.
3.
4.
12.4.1
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again
configured for the PWM mode of operation with the
additional feature of input Fault protection. While in this
mode, if a logic ‘0’ is detected on the OCFA/B pin, the
respective PWM output pin is placed in the high
impedance input state. The OCFLT bit (OCxCON<4>)
indicates whether a Fault condition has occurred. This
state is maintained until both of the following events
have occurred:
• The external Fault condition has been removed.
• The PWM mode has been re-enabled by writing
value of 0x0000.
and OCxRS (x denotes channel 1 to N) Compare
registers, respectively.
greater than value in OCxRS Compare register.
to the appropriate control bits.
Set the PWM period by writing to the appropriate
period register.
Set the PWM duty cycle by writing to the OCxRS
register.
Configure the output compare module for PWM
operation.
Set the TMRx prescale value and enable the
Timer, TON bit (TxCON<15>) = 1.
Simple PWM Mode
CONTINUOUS PULSE MODE
INPUT PIN FAULT PROTECTION
FOR PWM
© 2010 Microchip Technology Inc.
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