DSPIC30F3012-30I/ML Microchip Technology, DSPIC30F3012-30I/ML Datasheet - Page 32

• Manufacturer Part Number: DSPIC30F3012-30I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• For Use With: XLT44QFN5 - SOCKET TRANS ICE 18DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301230IML

dsPIC30F2011/2012/3012/3013
3.1.1
This architecture fetches 24-bit wide program memory.
Consequently,
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see
Access from Program Memory Using Program
Space
instructions offer a direct method of reading or writing
the lsw of any address within program space, without
going through data space. The TBLRDH and TBLWTH
instructions are the only method whereby the upper 8
bits of a program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the lsw, and TBLRDH
and TBLWTH access the space which contains the
MSB.
Figure 3-2
operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-3:
DS70139G-page 32
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Visibility”).
shows how the EA is created for table
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
PC Address
0x000000
0x000002
0x000004
0x000006
instructions
PROGRAM DATA TABLE ACCESS (lsw)
The
TBLRDL
00000000
00000000
00000000
00000000
are
Section 3.1.2 “Data
always
and
23
TBLWTL
aligned.
TBLRDL.W
16
A set of table instructions are provided to move byte or
word-sized data to and from program space. See
Figure 3-4 and Figure 3-5.
1.
2.
3.
4.
TBLRDL: Table Read Low
Word: Read the LS Word of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSB of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to
“Flash Program Memory”
Programming)
TBLRDH: Table Read High
Word: Read the MS Word of the program address;
P<23:16> maps to D<7:0>; D<15:8> will always
be = 0.
Byte: Read one of the MSB of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to
“Flash Program Memory”
Programming)
TBLRDL.B (Wn<0> = 1)
8
TBLRDL.B (Wn<0> = 0)
© 2010 Microchip Technology Inc.
for details on Flash
for details on Flash
0
Section 5.0
Section 5.0