DSPIC30F3012-30I/ML Microchip Technology, DSPIC30F3012-30I/ML Datasheet - Page 73

• Manufacturer Part Number: DSPIC30F3012-30I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• For Use With: XLT44QFN5 - SOCKET TRANS ICE 18DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301230IML

9.0
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1
16-bit Timer1 module. The following sections provide
detailed descriptions including setup and Control
registers, along with associated block diagrams for the
operational modes of the timers.
The Timer1 module is a 16-bit timer that serves as the
time counter for the real-time clock or operates as a
free-running interval timer/counter. The 16-bit timer has
the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
These operational characteristics are supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
• Interrupt on 16-bit Period register match or falling
FIGURE 9-1:
© 2010 Microchip Technology Inc.
Note:
modes
edge of external gate signal
TIMER1 MODULE
SOSCO/
T1IF
Event Flag
depicts the simplified block diagram of the
SOSCI
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
T1CK
TGATE
16-BIT TIMER1 MODULE BLOCK DIAGRAM
0
1
Reset
Equal
LPOSCEN
dsPIC30F2011/2012/3012/3013
Comparator x 16
TMR1
PR1
Q
Q
Gate
Sync
CK
T
CY
D
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON.
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value preloaded into the Period register PR1, then
resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer module logic resumes the incre-
menting sequence on termination of CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the respective TSIDL bit = 0. If
TSIDL = 1, the timer module logic resumes the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer stops incrementing if TSIDL = 1.
TGATE
1 x
0 1
0 0
TON
TSYNC
1
0
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
DS70139G-page 73
Figure 9-1