PIC18F2331-I/SP Microchip Technology, PIC18F2331-I/SP Datasheet - Page 222

• Manufacturer Part Number: PIC18F2331-I/SP
• Description: IC PIC MCU FLASH 4KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
18.3.2
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is
disabled. The Stop (P) and Start (S) bits will toggle
based on the Start and Stop conditions. Control of the
I
is Idle and both the S and P bits are clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<5:4> or
TRISD<3:2> bits. The output level is always low, irre-
spective
PORTD<3:2>. So when transmitting data, a '1' data bit
must have the TRISC<4> bit set (input) and a '0' data
bit must have the TRISC<4> bit cleared (output). The
same scenario is true for the SCL line with the
TRISC<4> or TRISD<2> bit. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 18-3:
DS39616B-page 220
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
TRISD
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by SSP
Note 1:
2
C bus may be taken when the P bit is set, or the bus
Name
2:
3:
(3)
(3)
of
module in I
PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
Maintain these bits clear in I
Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD.
MASTER MODE
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
PORTC Data Direction Register
PORTD Data Direction Register
PSPIE
PSPIF
SMP
WCOL
Bit 7
the
GIE
2
C module.
REGISTERS ASSOCIATED WITH I
(2)
(1)
(1)
value(s)
2
SSPOV SSPEN
C mode.
CKE
ADIF
ADIE
Bit 6
PEIE
(2)
in
TMR0IE INTE
RCIF
RCIE
Bit 5
D/A
PORTC<5:4>
2
2
C mode) Address Register
C mode.
TXIE
Bit 4
TXIF
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
SSPIE CCP1IE TMR2IE TMR1IE
Preliminary
SSPIF CCP1IF TMR2IF TMR1IF
RBIE
Bit 3
or
S
2
TMR0IF
C OPERATION
Bit 2
R/W
18.3.3
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions, allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I
is set, or the bus is Idle and both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<5:4> or TRISD<3:2> ). There are
two stages where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to retransfer the data at a
later time.
INTF
Bit 1
2
UA
C bus may be taken when bit P (SSPSTAT<4>)
MULTI-MASTER MODE
Bit 0
RBIF
BF
 2003 Microchip Technology Inc.
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
Value on:
POR,
BOR
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
Value on
all other
Resets