PIC18F2331-I/SP Microchip Technology, PIC18F2331-I/SP Datasheet - Page 296

• Manufacturer Part Number: PIC18F2331-I/SP
• Description: IC PIC MCU FLASH 4KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39616B-page 294
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit =
REG
W
Carry bit =
REG
W
Q1
=
=
=
=
register 'f'
ADD W and Carry bit to f
[ label ] ADDWFC
0
d
a
(W) + (f) + (C)
N, OV, C, DC, Z
Add W, the Carry Flag and data
memory location ‘f’. If ‘d’ is 0, the
result is placed in W. If ‘d’ is 1, the
result is placed in data memory loca-
tion ‘f’. If ‘a’ is 0, the Access Bank
will be selected. If ‘a’ is 1, the BSR
will not be overridden.
1
1
ADDWFC
Read
Q2
0010
1
0x02
0x4D
0
0x02
0x50
f
[0,1]
[0,1]
255
00da
REG, W
Process
Data
Q3
dest
ffff
f [,d [,a]]
destination
Write to
Q4
ffff
Preliminary
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
Read literal
=
=
AND literal with W
[ label ] ANDLW
0
(W) .AND. k
N, Z
The contents of W are ANDed with
the 8-bit literal ‘k’. The result is
placed in W.
1
1
ANDLW
0000
Q2
‘k’
0xA3
0x03
k
 2003 Microchip Technology Inc.
255
1011
0x5F
Process
Data
Q3
W
k
kkkk
Write to W
Q4
kkkk