DSPIC30F3014-20I/ML Microchip Technology, DSPIC30F3014-20I/ML Datasheet - Page 158
DSPIC30F3014-20I/ML
Manufacturer Part Number
DSPIC30F3014-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F3014-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301420IML
- DSPIC30F3014-30IPT PDF datasheet
- DSPIC30F3014-30IPT PDF datasheet #2
- DSPIC30F3014-30IPT PDF datasheet #3
- DSPIC30F3014-30IPT PDF datasheet #4
- DSPIC30F3014-30IPT PDF datasheet #5
- DSPIC30F3014-20IP PDF datasheet #6
- Current page: 158 of 228
- Download datasheet (2Mb)
TABLE 20-7:
TABLE 20-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
2:
3:
4:
1:
2:
3:
4:
Addr.
0740
0742
0744
0770
0772
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reset state depends on type of Reset.
Reset state depends on Configuration bits.
These bits are not available in dsPIC30F3014 devices.
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
Reserved bits read as ‘1’ and must be programmed as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
IC8MD
T5MD
TRAPR
Bit 15
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
—
—
FWDTEN
MCLREN
BKBUG
(4)
Bit 15
(4)
FCKSM<1:0>
—
—
—
IOPUWR
IC7MD
T4MD
Bit 14
—
(4)
(4)
COSC<2:0>
Bit 14
COE
—
—
—
—
—
Bit 13
BGST LVDEN
T3MD
—
—
Bit 13
Bit 12 Bit 11
T2MD
—
—
—
—
—
Reserved
Reserved
—
—
T1MD
Bit 12
—
—
—
(3)
(3)
—
—
—
—
—
Bit 10
—
—
—
Bit 11
LVDL<3:0>
—
—
—
—
—
—
—
NOSC<2:0>
IC2MD
Bit 9
—
—
PWMPIN
(1)
Bit 10
—
—
—
—
—
(1)
DCIMD
IC1MD
Bit 8
(2)
—
FOS<2:0>
(4)
HPOL
Bit 9
I2CMD U2MD
—
—
—
—
EXTR
Bit 7
POST<1:0>
Reserved
—
—
(2)
Reserved
SWR SWDTEN WDTO
Bit 6
LPOL
—
—
Bit 8
(3)
—
—
—
(2)
(3)
LOCK
U1MD
Bit 5
—
—
BOREN
Bit 7
—
—
—
—
—
—
Bit 4
—
—
—
—
Bit 6
—
—
—
—
—
—
—
OC4MD
SPI1MD
SLEEP
TUN3
Bit 3
CF
(4)
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
OC3MD
TUN2
Bit 2
IDLE
—
—
Bit 4
(4)
—
—
—
—
LPOSCEN OSWEN
OC2MD
C1MD
TUN1
Bit 1
BOR
Bit 3
—
—
—
ADCMD 0000 0000 0000 0000
OC1MD 0000 0000 0000 0000
TUN0
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
0000 0000 0000 0000
(4)
Reset State
(3)
(3)
Bit 1
GCP
(Note 2)
(Note 3)
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0
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