DSPIC30F3011-20I/ML Microchip Technology, DSPIC30F3011-20I/ML Datasheet - Page 91
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3011-20I/ML
Manufacturer Part Number
DSPIC30F3011-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301120IML
- DSPIC30F3010-30ISO PDF datasheet
- DSPIC30F3010-30ISO PDF datasheet #2
- DSPIC30F3010-30ISO PDF datasheet #3
- DSPIC30F3010-30ISO PDF datasheet #4
- DSPIC30F3010-30ISO PDF datasheet #5
- DSPIC30F3010-20ISP PDF datasheet #6
- Current page: 91 of 228
- Download datasheet (4Mb)
14.0
This section describes the Quadrature Encoder
Interface (QEI) module and associated operational
modes. The QEI module provides the interface to
incremental encoders for obtaining mechanical position
data.
FIGURE 14-1:
© 2010 Microchip Technology Inc.
Note:
QEA
QEB
INDX
Note 1:
QUADRATURE ENCODER
INTERFACE (QEI) MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Synchronize
Sleep Input
In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software.
Det
UPDN_SRC
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
Programmable
Programmable
Programmable
0
1
Digital Filter
Digital Filter
Digital Filter
QEICON<11>
3
T
QEIM<2:0>
CY
Interface Logic
TQCS
Quadrature
Encoder
1
0
Up/Down
Mode Select
QEIM<2:0>
3
(1)
TQGATE
1
0
2
The operational features of the QEI include:
• Three input channels for two phase signals and
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-Bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
These operating modes are determined by setting the
appropriate
Figure 14-1
block diagram.
index pulse
dsPIC30F3010/3011
16-Bit Up/Down Counter
Max Count Register
D
CK
Comparator/
Zero Detect
(POSCNT)
(MAXCNT)
depicts the Quadrature Encoder Interface
TQCKPS<1:0>
Q
Q
1, 8, 64, 256
bits
Prescaler
2
QEIM<2:0>
Reset
Equal
(QEICON<10:8>).
DS70141F-page 91
QEIIF
Event
Flag
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