PIC18F2220-I/SO Microchip Technology, PIC18F2220-I/SO Datasheet - Page 86

• Manufacturer Part Number: PIC18F2220-I/SO
• Description: IC MCU FLASH 2KX16 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2220-I/SO

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Height: 2.31 mm
• Length: 17.87 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Details

PIC18F2220/2320/4220/4320
7.7
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write opera-
tions are disabled if either of these mechanisms are
enabled.
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
TABLE 7-1:
DS39599G-page 84
INTCON
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
LOOP
Name
Operation During Code-Protect
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
BRA
BCF
BSF
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
Loop
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
PEIE/GIEL TMR0IE
CFGS
CMIP
CMIE
CMIF
Bit 6
Bit 5
—
—
—
—
FREE
Bit 4
INTE
EEIP
EEIF
EEIE
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
7.8
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
Note:
Bit 2
Using the Data EEPROM
TMR3IP
TMR3IE
TMR3IF
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
Bit 1
INTF
WR
CCP2IP 11-1 1111 ---1 1111
CCP2IF 00-0 0000 ---0 0000
CCP2IE 00-0 0000 ---0 0000
Bit 0
RBIF
RD
© 2007 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xx-0 x000 uu-0 u000
POR, BOR
Value on:
—
Value on
all other
Resets
—