AT91SAM7S321-MU Atmel, AT91SAM7S321-MU Datasheet - Page 503
AT91SAM7S321-MU
Manufacturer Part Number
AT91SAM7S321-MU
Description
MCU ARM 32K HI SPD FLASH 64-QFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S321-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S321-MU
Manufacturer:
ATMEL
Quantity:
9 500
- Current page: 503 of 779
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35.5.1.3
6175K–ATARM–30-Aug-10
USB Transfer Event Definitions
As indicated below, transfers are sequential events carried out on the USB bus.
Table 35-3.
Notes:
A status transaction is a special type of host-to-device transaction used only in a control transfer.
The control transfer must be performed using endpoints with no ping-pong attributes. According
to the control sequence (read or write), the USB device sends or receives a status transaction.
Control Transfers
Interrupt IN Transfer
(device toward host)
Interrupt OUT Transfer
(host toward device)
Isochronous IN Transfer
(device toward host)
Isochronous OUT Transfer
(host toward device)
Bulk IN Transfer
(device toward host)
Bulk OUT Transfer
(host toward device)
1. Control transfer must use endpoints with no ping-pong attributes.
2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.
USB Transfer Events
(1) (3)
(2)
(2)
AT91SAM7S Series Preliminary
• Setup transaction > Data IN transactions > Status
• Setup transaction > Data OUT transactions > Status
• Setup transaction > Status IN transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
• Data IN transaction > Data IN transaction
• Data OUT transaction > Data OUT transaction
OUT transaction
IN transaction
503
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