ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 60

• Manufacturer Part Number: ATMEGA16L-8PU
• Description: IC AVR MCU 16K 8MHZ 3V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.7-5.5 V
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

60
ATmega16(L)
Table 26. Overriding Signals for Alternate Functions in PB7..PB4
Table 27. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PB7/SCK
SPE • MSTR
PORTB7 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
0
0
SCK INPUT
–
PB3/OC0/AIN1
0
0
0
0
OC0 ENABLE
OC0
0
0
–
AIN1 INPUT
PB6/MISO
SPE • MSTR
PORTB6 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
0
0
SPI MSTR INPUT
–
PB2/INT2/AIN0
0
0
0
0
0
0
INT2 ENABLE
1
INT2 INPUT
AIN0 INPUT
PB1/T1
0
0
0
0
0
0
0
0
T1 INPUT
–
PB5/MOSI
SPE • MSTR
PORTB5 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
0
0
SPI SLAVE INPUT
–
PB0/T0/XCK
0
0
0
0
UMSEL
XCK OUTPUT
0
0
XCK INPUT/T0 INPUT
–
PB4/SS
SPE • MSTR
PORTB4 • PUD
SPE • MSTR
0
0
0
0
0
SPI SS
–
2466R–AVR–06/08