DSPIC30F2010-30I/SOG Microchip Technology, DSPIC30F2010-30I/SOG Datasheet - Page 197

• Manufacturer Part Number: DSPIC30F2010-30I/SOG
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SOG

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201030ISO

TimerQ (QEI Module) External Clock
Timing Characteristics
Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
 2004 Microchip Technology Inc.
Timing Characteristics .............................................. 167
A/D Conversion
Bandgap Start-up Time............................................. 164
CLKOUT and I/O....................................................... 161
External Clock........................................................... 157
I
I
Input Capture (CAPX) ............................................... 168
Motor Control PWM Module...................................... 170
Motor Control PWM Module Falult............................ 170
OC/PWM Module ...................................................... 169
Oscillator Start-up Timer ........................................... 162
Output Compare Module........................................... 168
Power-up Timer ........................................................ 162
QEI Module Index Pulse ........................................... 172
Reset......................................................................... 162
SPI Module
TimerQ (QEI Module) External Clock ....................... 167
Type A, B and C Timer External Clock ..................... 165
Watchdog Timer........................................................ 162
Center Aligned PWM .................................................. 85
Dead-Time .................................................................. 86
Edge Aligned PWM..................................................... 84
PWM Output ............................................................... 73
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy............... 159
A/D Conversion
Bandgap Start-up Time............................................. 164
Brown-out Reset ....................................................... 163
CLKOUT and I/O....................................................... 161
External Clock........................................................... 158
I
I
Input Capture ............................................................ 168
Motor Control PWM Module...................................... 170
Oscillator Start-up Timer ........................................... 163
Output Compare Module........................................... 168
Power-up Timer ........................................................ 163
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode)..................................... 179
C Bus Data (Slave Mode)....................................... 181
10-Bit High-speed (CHPS = 01,
10-bit High-speed (CHPS = 01,
Master Mode ..................................................... 178
Slave Mode ....................................................... 180
Master Mode ..................................................... 178
Slave Mode ....................................................... 180
Master Mode (CKE = 0) .................................... 173
Master Mode (CKE = 1) .................................... 174
Slave Mode (CKE = 0) ...................................... 175
Slave Mode (CKE = 1) ...................................... 176
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
High-speed ....................................................... 186
SIMSAM = 0, ASAM = 0,
SSRC = 000) ............................................ 184
SIMSAM = 0, ASAM = 1,
SSRC = 111, SAMC = 00001) .................. 185
DD
).......................................... 126
DD
DD
), Case 1...................... 126
), Case 2...................... 126
Preliminary
Timing Specifications
U
UART
Unit ID Locations .............................................................. 119
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 119
Wake-up from Sleep and Idle ............................................. 41
Watchdog Timer
Watchdog Timer (WDT)............................................ 119, 129
WWW, On-Line Support ....................................................... 4
QEI Module
Quadrature Decoder................................................. 171
Reset ........................................................................ 163
Simple OC/PWM Mode ............................................ 169
SPI Module
Type A Timer External Clock.................................... 165
Type B Timer External Clock.................................... 166
Type C Timer External Clock.................................... 166
Watchdog Timer ....................................................... 163
PLL Clock ................................................................. 159
Address Detect Mode ............................................... 107
Auto Baud Support ................................................... 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART ................................ 105
Loopback Mode ........................................................ 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data ......................................................... 106
Reception Error Handling ......................................... 106
Transmitting Data ..................................................... 105
UART1 Register Map ............................................... 109
Timing Characteristics .............................................. 162
Timing Requirements ............................................... 163
Enabling and Disabling............................................. 129
Operation.................................................................. 129
External Clock .................................................. 167
Index Pulse....................................................... 172
Master Mode (CKE = 0).................................... 173
Master Mode (CKE = 1).................................... 174
Slave Mode (CKE = 0)...................................... 175
Slave Mode (CKE = 1)...................................... 177
Alternate I/O ..................................................... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and Stop Bit
In 8-bit or 9-bit Data Mode................................ 106
Interrupt ............................................................ 106
Receive Buffer (UxRCB)................................... 106
Framing Error (FERR) ...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR) .......................................... 107
Receive Break .................................................. 107
Receive Buffer Overrun Error (OERR Bit) ........ 106
In 8-bit Data Mode ............................................ 105
In 9-bit Data Mode ............................................ 105
Interrupt ............................................................ 106
Transmit Buffer (UxTXB) .................................. 105
Selections................................................. 105
dsPIC30F2010
DS70118E-page 195