DSPIC30F2010-30I/SOG Microchip Technology, DSPIC30F2010-30I/SOG Datasheet - Page 89

• Manufacturer Part Number: DSPIC30F2010-30I/SOG
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SOG

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201030ISO

14.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains six
bits, POVDxH<3:1> and POVDxL<3:1>, that determine
which PWM I/O pins will be overridden. The lower half
of
POUTxH<3:1> and POUTxL<3:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
14.10.1
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead time insertion is still performed when PWM
channels are overridden manually.
14.10.2
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge Aligned mode, when PTMR is zero.
• Center Aligned modes, when PTMR is zero and
14.11 PWM Output and Polarity Control
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three bits in the FPORBOR configuration regis-
ter (see Section 21) work in conjunction with the three
PWM enable bits (PWMEN<3:1>) located in the
PWMCON1 SFR. The configuration bits and PWM
enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs. The PWMPIN con-
figuration fuse allows the PWM module outputs to be
optionally enabled on a device Reset. If PWMPIN = 0,
the PWM outputs will be driven to their inactive states
at Reset. If PWMPIN = 1 (default), the PWM outputs
will be tri-stated. The HPOL bit specifies the polarity for
the PWMxH outputs, whereas the LPOL bit specifies
the polarity for the PWMxL outputs.
 2004 Microchip Technology Inc.
when the value of PTMR matches PTPER.
the
OVDCON
OVERRIDE SYNCHRONIZATION
COMPLEMENTARY OUTPUT MODE
register
contains
six
bits,
Preliminary
14.11.1
The PEN<3:1>H and PEN<3:1>L control bits in the
PWMCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a partic-
ular PWM output pin not enabled, it is treated as a
general purpose I/O pin.
14.12 PWM FLTA Pins
There is one FLTA pin (FLTA) associated with the PWM
module. When asserted, this pin can optionally drive
each of the PWM I/O pins to a defined state.
14.12.1
The FLTACON SFR has 4 control bits that determine
whether a particular pair of PWM I/O pins is to be con-
trolled by the FLTA input pin. To enable a specific PWM
I/O pin pair for FLTA overrides, the corresponding bit
should be set in the FLTACON register.
If all enable bits are cleared in the FLTACON register,
then the FLTA input pin has no effect on the PWM mod-
ule and the pin may be used as a general purpose inter-
rupt or I/O pin.
14.12.2
The FLTACON special function register has 8 bits that
determine the state of each PWM I/O pin when it is
overridden by a FLTA input. When these bits are
cleared, the PWM I/O pin is driven to the inactive state.
If the bit is set, the PWM I/O pin will be driven to the
active state. The active and inactive states are refer-
enced to the polarity defined for each PWM I/O pin
(HPOL and LPOL polarity control bits).
Note:
OUTPUT PIN CONTROL
FAULT PIN ENABLE BITS
The FLTA pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON register are cleared, then
the FLTA pin(s) could be used as general
purpose interrupt pin(s). Each FLTA pin
has an interrupt vector, interrupt flag bit
and interrupt priority bits associated with it.
FAULT STATES
dsPIC30F2010
DS70118E-page 87