ATMEGA169P-16AU Atmel, ATMEGA169P-16AU Datasheet
ATMEGA169P-16AU
Specifications of ATMEGA169P-16AU
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ATMEGA169P-16AU Summary of contents
Page 1
... I/O and Packages – 54 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN • Speed Grade: – ATmega169PV MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega169P MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
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... Pin Configurations 1.1 Pinout - TQFP/QFN/MLF Figure 1-1. 64A (TQFP) and 64M1 (QFN/MLF) Pinout ATmega169P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 ...
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... Pinout - DRQFN Figure 1-2. 64MC (DRQFN) Pinout ATmega169P Top view Table 1-1. DRQFN-64 Pinout ATmega169P. A1 PE0 A9 B1 VLCDCAP B8 A2 PE1 A10 B2 PE2 B9 A3 PE3 A11 B3 PE4 B10 A4 PE5 A12 B4 PE6 B11 A5 PE7 A13 B5 PB0 B12 A6 PB1 A14 B6 PB2 B13 A7 PB3 ...
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... Overview The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Atmel ATmega169P is a powerful microcontroller that provides a highly flex- ible and cost effective solution to many embedded control applications. The ATmega169P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 8018P– ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega169P as listed on ”Alternate Functions of Port A” on page 2.2.4 Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega169P as listed on ”Alternate Functions of Port E” on page 2.2.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter ...
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... An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in ure 23-2 on page capacitance reduces ripple on V 8018P–AVR–08/10 236. This capacitor acts as a reservoir for LCD power (V but increases the time until V LCD ATmega169P Fig large LCD reaches its target value. LCD 8 ...
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... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8018P–AVR–08/10 1. ATmega169P 9 ...
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... These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 8018P–AVR–08/10 ATmega169P 10 ...
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... The program memory is In-System Reprogrammable Flash memory. 8018P–AVR–08/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega169P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega169P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or Decremented by 2 interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega169P Figure 13 ...
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... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega169P – – SP10 SP9 SP4 SP3 ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 8018P–AVR–08/10 for details. ”Interrupts” on page 56 ”Boot Loader Support – Read-While-Write Self-Programming” on page ATmega169P ”Memory Program- ”Interrupts” on page 56. The list also for more information. 15 ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8018P–AVR–08/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega169P 16 ...
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... Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8018P–AVR–08/ R/W R/W R/W R ⊕ V ATmega169P R/W R/W R/W R SREG 17 ...
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... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-4, each register is also assigned a data memory address, mapping them ATmega169P 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 8018P–AVR–08/10 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATmega169P Figure 6- R26 (0x1A R28 (0x1C R30 (0x1E ...
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... For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega169P Program Counter (PC bits wide, thus addressing the 8K program memory locations. The ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1,024 bytes of internal data SRAM in the ATmega169P are all accessible through all these addressing modes. The Register File is described in 18 ...
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... This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 7-3. 8018P–AVR–08/10 On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ATmega169P cycles as described in Figure CPU T2 T3 Address valid Next Instruction 7-3. 22 ...
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... EEPROM Data Memory The ATmega169P contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. This section describes the access between the EEPROM and the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 7-1. Symbol EEPROM write (from CPU) 8018P–AVR–08/10 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 27 072 ATmega169P Table 7-1 lists the typical pro- Typical Programming Time 3 ...
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... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega169P 25 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; ATmega169P 26 ...
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... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... General Purpose I/O Registers The ATmega169P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Sta- tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit- accessible using the SBI, CBI, SBIS, and SBIC instructions ...
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... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. 8018P–AVR–08/ MSB R/W R/W R/W R – – – – ATmega169P LSB R/W R/W R/W R EERIE EEMWE EEWE EERE R/W R/W R/W R EEDR EECR ...
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... LCD Controller Timer/Counter Modules clk I/O clk ASY Timer/Counter External Clock Oscillator is halted, enabling USI start condition detection in all sleep modes. I/O ATmega169P CPU Core RAM clk AVR Clock CPU Control Unit clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock ...
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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 338. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ATmega169P (1) CKSEL3:0 1111 - 1000 0111 - 0110 0011, 0001, 0101, 0100 ”Typical Charac- = 3.0V) Number of Cycles CC 4 ...
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... Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved 1. The device is shipped with this option selected ATmega169P for more details. The device is shipped for more details. ”OSCCAL – Oscillator Calibration Register” on Table 28-2 on page 299. (1)(3) CKSEL3:0 ...
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... Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 This option should not be used with crystals, only with ceramic resonators. ATmega169P Figure 8-2. Either a quartz crystal or a XTAL2 (TOSC2) XTAL1 (TOSC1) GND Table 8-5. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega169P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 8-7 Table 8-7 ...
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... Additional Delay from Reset ( Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application ATmega169P Cap (Xtal1/Tosc1) Cap (Xtal2/Tosc2 ⋅ – s Figure 8-2 on page 33 ...
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... Crystal Oscillator Clock Frequency Frequency Range MHz Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from down and Power-save Reset ( ATmega169P XTAL2 XTAL1 GND = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4.1 ms Fast rising power 14CK + 65 ms ...
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... Oscillator. See crystal requirements. ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source ...
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... R/W R/W R/W Device Specific Calibration Value Table 28-2 on page 332. The application software can write this register to change 332. Calibration outside that range is not guaranteed CLKPCE – – R 39. ATmega169P CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 R R/W ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 8-13. CLKPS3 8018P–AVR–08/10 Clock Prescaler Select CLKPS2 CLKPS1 ATmega169P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 39 ...
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... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8018P–AVR–08/10 presents the different clock systems in the ATmega169P, and their distri- Oscillators (2) X ...
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... The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in 8018P–AVR–08/10 and clk , while allowing the other clocks to run. CPU FLASH , clk , and clk I/O CPU ”Clock Sources” on page ATmega169P , while allowing the FLASH ”External Interrupts” on page 61 31. 41 ...
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... Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See sleep modes, the clock is already stopped. 8018P–AVR–08/10 ”PRR – Power Reduction Register” on page ”Supply Current of I/O modules” on page 343 ATmega169P 45, pro- for examples. In all other 42 ...
Page 43
... Analog Comparator” on page 212 for details on the start-up time. ”Watchdog Timer” on page 51 for details on how to configure the Watchdog Timer. ATmega169P ”ADC - Analog to Digital Converter” on page for details on how to configure the Ana- ”Brown-out Detection” on page 50 ”Internal Volt- ...
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... Input Enable and Sleep Modes” on page 69 /2, the input buffer will use excessive power input pin can cause significant current even in active mode. Digital CC ”DIDR1 – Digital Input Disable Register 1” on page 215 for details. ATmega169P for details on and ”DIDR0 – Digital 44 ...
Page 45
... SM0 Standby mode is only recommended for use with external crystals or resonators – – – ATmega169P – SM2 SM1 SM0 R R/W R/W R Table Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby Reserved PRLCD PRTIM1 PRSPI PRUSART0 R/W R/W R/W ...
Page 46
... Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. Note: 8018P–AVR–08/10 The Analog Comparator is disabled using the ACD-bit in the and Status Register” on page 214. ATmega169P ”ACSR – Analog Comparator Control 46 ...
Page 47
... Reset Sources The ATmega169P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 48
... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega169P DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 333. The POR is activated whenever CC 48 ...
Page 49
... MCU after the Time-out period – t Figure 10-4. External Reset During Operation 8018P–AVR–08/10 V POT V CC RESET RESET ”System and Reset Characteristics” on page CC ATmega169P V RST t TOUT 333) will generate a – on its positive edge, the RST – has expired. TOUT 49 ...
Page 50
... Brown-out Detection ATmega169P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega169P resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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... WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 8018P–AVR–08/10 WATCHDOG OSCILLATOR ATmega169P 52 ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret (1) /* Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See ”About Code Examples” on page ATmega169P 10. 53 ...
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... Watchdog Timer” on page 52. 8018P–AVR–08/ – – – JTRF R – – – WDCE R See ”Timed Sequences for Changing the Configuration of the ATmega169P WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description WDE WDP2 WDP1 WDP0 R/W R/W R/W R MCUSR WDTCR 54 ...
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... Also see Figure 29-54 on page 366. ATmega169P Typical Time-out at Typical Time-out 3. 5. 15.4 ms 14.7 ms 30.8 ms 29.3 ms 61.6 ms 58.7 ms 0.12 s 0.12 s 0.25 s 0.23 s 0. ...
Page 56
... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega169P. For a general explanation of the AVR interrupt handling, refer to page 15. 11.1 Interrupt Vectors in ATmega169P Table 11-1. Vector No Notes: 8018P–AVR–08/10 Reset and Interrupt Vectors Program (2) Address Source (1) 0x0000 RESET 0x0002 ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega169P is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 ...
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... RESET jmp EXT_INT0 jmp PCINT0 ... ... jmp SPM_RDY ATmega169P ; Enable interrupts Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ; Set Stack Pointer to top of RAM ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 280 ATmega169P ; Set Stack Pointer to top of RAM ; Enable interrupts 60. ...
Page 60
... Space” on page 8018P–AVR–08/10 uchar temp; temp = MCUCR; MCUCR = temp | (1<<IVCE); */ MCUCR = temp | (1<<IVSEL JTD - - R for details. 59. See Code Example. ATmega169P PUD – – IVSEL R R ”Boot Loader Support – Read-While-Write ”Moving Interrupts Between Application and Boot 0 ...
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... An example of timing of a pin change interrupt is shown in Figure 12-1. Pin Change Interrupt 8018P–AVR–08/10 ”Clock Systems and their Distribution” on page pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATmega169P 30. Figure 12-1. pcint_in_(0) 0 pcint_syn pcint_setflag x clk 30. Low PCIF 61 ...
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... The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request PCIE1 PCIE0 – – R/W R ATmega169P – – ISC01 ISC00 R R R/W R – – ...
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... I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8018P–AVR–08/ PCIF1 PCIF0 – – R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega169P – – – INTF0 R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R EIFR PCMSK1 ...
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... If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8018P–AVR–08/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega169P PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 64 ...
Page 65
... Ground as indicated in CC for a complete list of parameters. Pxn C pin ”Register Description for I/O-Ports” on page 71. Refer to the individual module sections for a full description of the alter- ATmega169P Figure 13-1 on page 65. Refer Logic See Figure "General Digital I/O" for Details 88. ” ...
Page 66
... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 88, the DDxn bits are accessed at the DDRx I/O address, the ATmega169P Figure 13-2 PUD Q D DDxn ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 13-2 on page shows a timing diagram of the synchronization when reading an externally applied pin ATmega169P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 68
... SYNC LATCH PINxn r17 Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega169P XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
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... Figure 13-2 on page 66, the digital input signal can be clamped to ground at the ”Alternate Port Functions” on page ATmega169P /2. CC 71. 69 ...
Page 70
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8018P–AVR–08/10 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega169P 70 ...
Page 71
... SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port Figure 13-5 on page 71 are not shown in the succeeding tables. The overriding ATmega169P Figure 13-2 on page 66 PUD Q ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega169P 72 ...
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... Figure 13-5 on page 71. Overriding Signals for Alternate Functions in PA7..PA4 PA7/SEG3 PA6/SEG2 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG3 SEG2 ATmega169P PA5/SEG1 PA4/SEG0 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG1 SEG0 73 ...
Page 74
... Interrupt12). MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11). MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10). SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9). SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8). ATmega169P PA1/COM1 PA0/COM0 LCDEN • LCDEN (LCDMUX> ...
Page 75
... PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source. • SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI is activated when this pin is driven 8018P–AVR–08/10 ATmega169P 75 ...
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... PCINT14 OC2A ENABLE OC1B ENABLE OC2A OC1B – – PCINT15 • PCIE1 PCINT14 • PCIE1 1 1 PCINT15 INPUT PCINT14 INPUT – – ATmega169P PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE OC1A OC0A – – PCINT13 • PCIE1 PCINT12 • PCIE1 1 1 ...
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... SEG8 (LCD Front Plane 8) PC3 SEG9 (LCD Front Plane 9) PC2 SEG10 (LCD Front Plane 10) PC1 SEG11 (LCD Front Plane 11) PC0 SEG12 (LCD Front Plane 12) ATmega169P PB1/SCK/ PB0/SS/ PCINT9 PCINT8 SPE • MSTR SPE • MSTR PORTB1 • PUD PORTB0 • PUD SPE • ...
Page 78
... SEG5 SEG6 PC3/SEG9 PC2/SEG10 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG9 SEG10 ATmega169P PC5/SEG7 PC4/SEG8 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG7 SEG8 PC1/SEG11 PC0/SEG12 LCDEN LCDEN ...
Page 79
... SEG15 (LCD front plane 15) SEG16 (LCD front plane 16) SEG17 (LCD front plane 17) SEG18 (LCD front plane 18) SEG19 (LCD front plane 19) SEG20 (LCD front plane 20) INT0/SEG21 (External Interrupt0 Input or LCD front plane 21) ICP1/SEG22 (Timer/Counter1 Input Capture pin or LCD front plane 22) ATmega169P Table 13-12. 79 ...
Page 80
... LCDEN • LCDEN • (LCDPM>3) (LCDPM> – – LCDEN • LCDEN • (LCDPM>3) (LCDPM> – – – – ATmega169P PD5/SEG17 PD4/SEG18 LCDEN • LCDEN • (LCDPM>2) (LCDPM> LCDEN • LCDEN • (LCDPM>2) (LCDPM> – – LCDEN • LCDEN • (LCDPM>2) (LCDPM> ...
Page 81
... USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4) AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3) XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input or Pin Change Interrupt2) TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1) RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0) ATmega169P Table 13-15. 81 ...
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... DO I/O – – PCINT7 • PCIE0 PCINT6 • PCIE0 1 1 PCINT7 INPUT PCINT6 INPUT – – 1. CKOUT is one if the CKOUT Fuse is programmed ATmega169P relates the alternate functions of Port E to the overrid- 71. PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE 0 0 USI_TWO-WIRE USI_TWO-WIRE (SDA + PORTE5) • ...
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... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega169P PE1/TXD/ PCINT1 TXENn 0 TXENn 1 ...
Page 84
... PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 1 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO – – JTAGEN JTAGEN 0 0 – – TDI ADC6 INPUT ADC7 INPUT ATmega169P PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN – – JTAGEN JTAGEN 0 1 – – TMS TCK ADC5 INPUT ...
Page 85
... T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23) T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24) SEG4 (LCD Front Plane 4) SEG13 (LCD Front Plane 13) SEG14 (LCD Front Plane 14) 1. Port G, PG5 is input only. Pull-up is always on. See Table 27-3 on page 297 for RSTDISBL fuse. ATmega169P PF1/ADC1 PF0/ADC0 ...
Page 86
... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8018P–AVR–08/10 and Table 13-22 relates the alternate functions of Port G to the overrid- Figure 13-5 on page 71. – – ATmega169P PG4/T0/SEG23 LCDEN • (LCDPM>5) 0 LCDEN • (LCDPM> – – LCDEN • (LCDPM> INPUT SEG23 86 ...
Page 87
... LCDEN • LCDEN (LCDPM> LCDEN • LCDEN (LCDPM> – – LCDEN • LCDEN (LCDPM> INPUT – SEG24 SEG4 ATmega169P PG1/SEG13 PG0/SEG14 LCDEN • LCDEN • (LCDPM>0) (LCDPM> LCDEN • LCDEN • (LCDPM>0) (LCDPM> – – LCDEN • LCDEN • (LCDPM>0) (LCDPM> – ...
Page 88
... PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega169P – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 ...
Page 89
... PIND4 R/W R/W R/W R/W N/A N/A N/A N PORTE7 PORTE6 PORTE5 PORTE4 R/W R/W R/W R DDE7 DDE6 DDE5 DDE4 R/W R/W R/W R ATmega169P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 90
... PORTG4 PORTG4 R – – DDG5 DDG4 R – – PING5 PING4 R N/A ATmega169P PINE3 PINE2 PINE1 PINE0 R/W R/W R/W R/W N/A N/A N/A N PORTF3 PORTF2 PORTF1 PORTF0 R/W R/W R/W R DDF3 DDF2 DDF1 DDF0 R/W R/W R/W R/W 0 ...
Page 91
... CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. 102. TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn ATmega169P ”8-bit Timer/Counter Register TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) Waveform OCn Generation ...
Page 92
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. ”Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn direction bottom ATmega169P 135. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 93
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 96. (See ”Modes of Operation” on page shows a block diagram of the Output Compare unit. ATmega169P in the following. T0 96.). 93 ...
Page 94
... This feature allows OCR0A to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 8018P–AVR–08/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega169P TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 94 ...
Page 95
... Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. 8018P–AVR–08/10 COMnx1 Waveform COMnx0 D Generator FOCn OCnx D PORT D DDR clk I/O ATmega169P Figure 14 OCn Pin shows a sim- 95 ...
Page 96
... See ”8-bit Timer/Counter Register Description” on page 102. Table 14-3 on page 103, and for phase correct PWM refer to (See ”Compare Match Output Unit” on page Figure ATmega169P 103. For fast PWM mode, refer to Table 14-5 on page 103. 95.). 14-8, ...
Page 97
... DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. 8018P–AVR–08/10 Figure clk_I ------------------------------------------------- - OCnx ⋅ ⋅ OCRnx 1 + ATmega169P 14-5. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 OC0 ) 97 = ...
Page 98
... The TCNT0 value is in the timing diagram shown as a his clk_I ----------------- - OCnxPWM N 256 = f OC0 ATmega169P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 Table 14-4 on page 103). The actual ⋅ /2 when OCR0A is set to zero. This clk_I/O 98 ...
Page 99
... PWM output can be generated by setting the COM0A1:0 to three (See The actual OC0A value will only be visible on the port pin if the data direction for the port pin is 8018P–AVR–08/ ATmega169P Figure 14-7. OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 100
... Figure 14-7 on page 99 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega169P f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low Figure 14-7 on page 99 ...
Page 101
... OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega169P /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 102
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega169P COM0A0 WGM01 CS02 CS01 R/W ...
Page 103
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 99 for more details. ATmega169P (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...
Page 104
... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R – – – ATmega169P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R – – – OCIE0A R TCNT0 ...
Page 105
... Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. 8018P–AVR–08/ – – – – ATmega169P – – OCF0A TOV0 R R R/W R TIFR0 105 ...
Page 106
... The PRTIM1 bit in to zero to enable Timer/Counter1 module. 8018P–AVR–08/10 Figure 1-1 on page Section 15.11 ”16-bit Timer/Counter Register Description” on page Section 9.9.2 ”PRR – Power Reduction Register” on page 45 ATmega169P Figure 15-1 on page 107. For 2. CPU accessible I/O Registers, 128. must be written ...
Page 107
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Table 13-5 on page Timer/Counter1 pin placement and description. ATmega169P (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 108
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega169P (See ”AC 108 ...
Page 109
... Therefore, when both 8018P–AVR–08/10 (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See ”About Code Examples” on page 10. ATmega169P 109 ...
Page 110
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See ”About Code Examples” on page 10. ATmega169P 110 ...
Page 111
... SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See ”About Code Examples” on page 10. ”Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega169P 135. 111 ...
Page 112
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ”Modes of Operation” on page ATmega169P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 118 ...
Page 113
... ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8018P–AVR–08/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega169P Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 114
... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 8018P–AVR–08/10 109. ATmega169P ”Accessing 16-bit Registers” (Figure 16-1 on page 135). The edge detector is also ...
Page 115
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega169P 118.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 116
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8018P–AVR–08/10 109. ATmega169P ”Accessing 16-bit Registers” 116 ...
Page 117
... Note that some COM1x1:0 bit settings are reserved for certain modes of operation. The COM1x1:0 bits have no effect on the Input Capture unit. 8018P–AVR–08/10 Waveform Generator I/O for details. See ”16-bit Timer/Counter Register Description” on page 128. ATmega169P Figure 15 OCnx ...
Page 118
... It also simplifies the opera- tion of counting external events. 8018P–AVR–08/10 Table 15-1 on page (See ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page ATmega169P 128. For fast PWM mode refer to 117.) Table 15-2 on Table 15-3 on 126. ...
Page 119
... MAX to 0x0000. 8018P–AVR–08/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega169P Figure 15-6. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 + 119 ...
Page 120
... OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A 8018P–AVR–08/10 ( TOP log R = ---------------------------------- - FPWM log ATmega169P ) + Figure 15-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 121
... OC1A toggle in CTC mode, except the double buffer feature of the Output Com- pare unit is enabled in the fast PWM mode. 8018P–AVR–08/10 Table 15-2 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O 1 ATmega169P 128). The actual ) 121 ...
Page 122
... Figure 15-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 8018P–AVR–08/ TOP log ---------------------------------- - PCPWM log ATmega169P Figure 15-8. The figure OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 122 ...
Page 123
... PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1 the OC1A output will toggle with a 50% duty cycle. 8018P–AVR–08/10 Figure 15-8 on page 122 f clk_I --------------------------- - OCnxPCPWM ⋅ ⋅ TOP ATmega169P illustrates, Table 15-3 on page 129). 123 ...
Page 124
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 8018P–AVR–08/10 and Figure 15-9 on page 125). log R = ---------------------------------- - PFCPWM Figure 15-9 on page ATmega169P ( ) TOP log 125. The figure shows phase and fre- Figure 15- 124 ...
Page 125
... The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). 8018P–AVR–08/ shows the output generated is, in contrast to the phase correct mode, symmetri OCnxPFCPWM ATmega169P OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 ...
Page 126
... I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the count sequence close to TOP in various modes. When ATmega169P ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O ...
Page 127
... I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega169P TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value ...
Page 128
... Compare Output Mode, Fast PWM COM1A0/COM1B0 special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. Mode” on page 120. for more details. ATmega169P COM1B0 – – WGM11 R R/W 0 ...
Page 129
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. ”Phase Correct PWM Mode” on page 122. Table 15-4 on page ATmega169P Description Normal port operation, OC1A/OC1B disconnected. WGM13 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 130
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega169P Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A BOTTOM ICR1 ...
Page 131
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R ATmega169P 126 – – – Figure 0 – TCCR1C R 0 131 ...
Page 132
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See ”Accessing 16-bit Registers” on page 109. ATmega169P R/W R/W R/W R See ”Accessing 16-bit R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...
Page 133
... ICIE1 (See ”Interrupts” on page 56.) is executed when the ICF1 Flag, located in TIFR1, is set. (See ”Interrupts” on page (See ”Interrupts” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega169P ICR1[15:8] ICR1[7:0] R/W R/W R/W R ...
Page 134
... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8018P–AVR–08/ – – ICF1 – R ATmega169P – OCF1B OCF1A TOV1 R R/W R/W R Table 15-4 on page 130 for the TOV1 ...
Page 135
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 shows a functional equivalent block diagram of the T1/T0 synchronization and /clk clk I/O Synchronization ATmega169P /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 16-1 ...
Page 136
... PSR10 T0 T1 Note: 8018P–AVR–08/10 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATmega169P (1) T1 T1/T0) is shown in Figure 16-1 on page /2.5. clk_I/O clk T0 135. 136 ...
Page 137
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8018P–AVR–08/ TSM – – – R ATmega169P – – PSR2 PSR10 GTCCR R R R/W R 137 ...
Page 138
... Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRnx Synchronized Status flags Status flags ASSRn asynchronous mode select (ASn) ATmega169P Figure 17-1. For the actual 2. CPU accessible I/O Registers, including I/O 153. TOVn (Int.Req.) clk Tn TOSC1 T/C Oscillator Prescaler TOSC2 clk OCnx I/O (Int ...
Page 139
... OCR2A Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 156. For details on clock sources and prescaler, see 152. shows a block diagram of the counter and its surrounding environment. ATmega169P See ”Output . When the AS2 I/O ”ASSR Figure 139 ...
Page 140
... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 143. 143). shows a block diagram of the Output Compare unit. ATmega169P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk top ...
Page 141
... OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is down counting. 8018P–AVR–08/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega169P TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 141 ...
Page 142
... The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. 8018P–AVR–08/10 Waveform Generator clk I/O See ”8-bit Timer/Counter Register Description” on page 153. ATmega169P Figure 17 OCnx ...
Page 143
... Table 17-3 on page 154, and for phase correct PWM refer to (See ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page ATmega169P 154. For fast PWM mode, refer to Table 17-5 on page 154. 142.) 148. ...
Page 144
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8018P–AVR–08/ clk_I ------------------------------------------------- - OCnx ⋅ ⋅ OCRnx 1 + Flag is set in the same timer clock cycle that the TOV2 ATmega169P OCnx Interrupt Flag Set (COMnx1 OC2A ) 144 = ...
Page 145
... The TCNT2 value is in the timing diagram shown as a his clk_I ----------------- - OCnxPWM N 256 = f oc2 clk_I/O ATmega169P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 Table 17-4 on page 154). The actual ⋅ /2 when OCR2A is set to zero. This fea- 145 ...
Page 146
... The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or 8018P–AVR–08/ ATmega169P Figure 17-7. OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 147
... Compare Match and hence the OCn change that would have happened on the way up. 8018P–AVR–08/10 f clk_I ----------------- - OCnxPCPWM ⋅ N 510 Figure 17-7 on page 146 OCn has a transition from high to low Figure 17-7 on page ATmega169P 146. When the OCR2A value 147 ...
Page 148
... TOVn shows the same timing data, but with the prescaler enabled. clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn shows the setting of OCF2A in all modes except CTC mode. ATmega169P should be replaced by I/O MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 148 ...
Page 149
... I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega169P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP /8) clk_I/O OCRnx + 2 149 ...
Page 150
... The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up 8018P–AVR–08/10 Enable interrupts, if needed. ATmega169P 150 ...
Page 151
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8018P–AVR–08/10 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega169P 151 ...
Page 152
... T2S Clear AS2 PSR2 CS20 CS21 CS22 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S ATmega169P 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S /8, clk T2S T2S as well as 0 (stop) may be selected ...
Page 153
... CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 17-3 on page 154 ATmega169P COM2A0 WGM21 CS22 CS21 ...
Page 154
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 146 for more details. ATmega169P (1) ”Fast PWM Mode” on page 144 (1) ”Phase Correct PWM Mode” on ...
Page 155
... T2S 1 0 clk clk TCNT2[7:0] R/W R/W R/W R OCR2A[7:0] R/W R/W R/W R ATmega169P /(No prescaling) /8 (From prescaler) /32 (From prescaler) /64 (From prescaler) /128 (From prescaler) /256 (From prescaler) /1024 (From prescaler R/W R/W R/W R R/W R/W R/W R Table TCNT2 OCR2A 155 ...
Page 156
... Timer Oscillator 1 (TOSC1) pin instead of a 8018P–AVR–08/ – – – – – – – – – – – EXCLK AS2 R/W R ATmega169P – – OCIE2A TOIE2 R R R/W R – – OCF2A TOV2 R R R/W R TCN2UB OCR2UB TCR2UB TIMSK2 TIFR2 ASSR 156 ...
Page 157
... TSM bit is set. Refer to the description of the chronization Mode” on page 137 8018P–AVR–08/ TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega169P . When AS2 is I – – PSR2 PSR10 GTCCR R R R/W R ”Bit 7 – TSM: Timer/Counter Syn- ...
Page 158
... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169P and peripheral devices or between several AVR devices. The PRSPI bit in enable SPI module. Figure 18-1. SPI Block Diagram Note: 8018P– ...
Page 159
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: High period: longer than 2 CPU clock cycles. 8018P–AVR–08/10 longer than 2 CPU clock cycles. ATmega169P Figure 18-2. The sys- SHIFT ENABLE 159 ...
Page 160
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See ”Alternate Functions of Port B” on page 74 direction of the user defined SPI pins. ATmega169P ”Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 160 ...
Page 161
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. ”About Code Examples” on page 10 ATmega169P 161 ...
Page 162
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. ”About Code Examples” on page ATmega169P 10. 162 ...
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... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 8018P–AVR–08/10 ATmega169P 163 ...
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... SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega169P 165, as done below: Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 ...
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... Figure 18-3 on page 164 and CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-3 on page 164 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega169P CPOL CPHA SPR1 SPR0 R/W R/W R/W R Figure 18-4 on page 164 for an example. The Trailing Edge ...
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... Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega169P is also used for program memory and EEPROM down- loading or uploading. See 8018P–AVR–08/10 Relationship Between SCK and the Oscillator Frequency ...
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... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8018P–AVR–08/ MSB R/W R/W R/W R ATmega169P LSB R/W R/W R/W R SPDR Undefined 167 ...
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... The PRUSART0 bit in enable USART0 module. A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. 8018P–AVR–08/10 ”PRR – Power Reduction Register” on page 45 ATmega169P must be written to zero to Figure 19-1 on page 169. CPU 168 ...
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... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Table 13-13 on page pin placement. ATmega169P Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
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... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 19-2 on page 171 8018P–AVR–08/10 Figure 19-1 on page shows a block diagram of the clock generation logic. ATmega169P 169) if the Buffer 170 ...
Page 171
... Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and ATmega169P U2X / ...
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... The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps). System Oscillator clock frequency. Contents of the UBRRHn and UBRRLn Registers, (0-4095). Figure 19-2 on page 171 depends on the stability of the system clock source therefore recommended to osc ATmega169P Equation for Calculating UBRRn (1) f OSC UBRRn = ...
Page 173
... Figure 19-4 on page 174 brackets are optional. 8018P–AVR–08/10 UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 19-3 shows, when UCPOLn is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside ATmega169P Sample Sample 173 ...
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... No transfers on the communication line (RxD or TxD). An IDLE line must be high. ⊕ even n 1 – ⊕ odd n 1 – Parity bit using even parity. even odd Parity bit using odd parity. Data bit n of the character. n ATmega169P FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
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... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. 8018P–AVR–08/10 ATmega169P 175 ...
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... USART_Init ( MYUBRR ); ... /* Set baud rate */ UBRRH0 = (unsigned char)(ubrr>>8); UBRRL0 = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBS0)|(3<<UCSZ00); 1. See ”About Code Examples” on page 10. ATmega169P 176 ...
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... UCSR0A,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data sts UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See ”About Code Examples” on page 10. ATmega169P 177 ...
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... Put data into buffer, sends the data */ UDR0 = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is used after initialization. 2. See ”About Code Examples” on page 10. ATmega169P 178 ...
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... The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo- ing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. 8018P–AVR–08/10 ATmega169P 179 ...
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... UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret (1) /* Wait for data to be received */ while ( !(UCSR0A & (1<<RXC0 Get and return received data from buffer */ return UDR0; 1. See ”About Code Examples” on page 10. ATmega169P 180 ...
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... FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. 8018P–AVR–08/10 ATmega169P 181 ...
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... UCSR0A; resh = UCSR0B; resl = UDR0 error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. ”About Code Examples” on page ATmega169P 10. 182 ...
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... Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see 8018P–AVR–08/10 ”Parity Bit Calculation” on page 174 ATmega169P and ”Parity Checker” on page 184. 183 ...
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... The following code example shows how to flush the receive buffer. Assembly Code Example USART_Flush: C Code Example void USART_Flush( void ) { } Note: 8018P–AVR–08/10 (1) sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush (1) unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; 1. See ”About Code Examples” on page 10. ATmega169P 184 ...
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... Double Speed mode. data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. 8018P–AVR–08/10 RxD IDLE Sample (U2X = Sample (U2X = ATmega169P START Figure 19-6 on page 186 shows the sampling of the Figure 19-5 BIT 0 ...
Page 186
... RxD Sample (U2X = Sample (U2X = Figure 19-7. For Double Speed mode the first low level must be delayed to 187) base frequency, the Receiver will not be able to synchronize the ATmega169P BIT ...
Page 187
... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega169P ( ) ----------------------------------- fast ( ) for normal speed and for normal speed and M Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ± ...
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... MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 8018P–AVR–08/10 ATmega169P 188 ...
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... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 8018P–AVR–08/10 ATmega169P 189 ...
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... Kbps 115.2 Kbps ATmega169P Table ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRRn Error UBRRn Error 95 0.0% 51 0.2% 47 ...
Page 191
... Kbps 0.5 Mbps ATmega169P f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
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... Kbps 1.3824 Mbps ATmega169P f = 14.7456 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 383 0.0% 767 0.0% 191 0.0% 383 0.0% 95 0.0% 191 0.0% 63 0.0% 127 0 ...
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... Mbps 2.304 Mbps ATmega169P f = 20.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 520 0.0% 1041 0.0% 259 0.2% 520 0.0% 129 0.2% 259 0. ...
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... The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). 8018P–AVR–08/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega169P R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA 194 ...
Page 195
... TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 8018P–AVR–08/10 ”Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega169P 188 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 195 ...
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... The 8018P–AVR–08/ – UMSELn UPMn1 UPMn0 R R/W R UMSELn Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega169P USBSn UCSZn1 UCSZn0 R/W R/W R/W R UCPOLn UCSRnC R/W 0 196 ...
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... UCSZn1 Transmitted Data Changed (Output of TxD Pin) Rising XCK Edge Falling XCK Edge ATmega169P Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD ...
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... Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRLn will trigger an immediate update of the baud rate prescaler. 8018P–AVR–08/ – – – – UBRRn[7: R/W R/W R/W R ATmega169P UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R UBRRHn UBRRLn 198 ...
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... Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, 207 USIDR 4-bit Counter 1 0 [1] USISR 2 USICR ATmega169P (Output only) DO (Input/Open Drain) DI/SDA TIM0 COMP 0 (Input/Open Drain) USCK/SCL 1 CLOCK HOLD Two-wire Clock Control Unit ”USI Regis- 199 ...
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... USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 8018P–AVR–08/10 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in Three-wire mode, one as Master and one as ATmega169P DO DI USCK DO DI USCK PORTxn 200 ...