PIC18C252-I/SP Microchip Technology, PIC18C252-I/SP Datasheet - Page 131
![IC MCU OTP 16KX16 A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18C252-I/SP
Manufacturer Part Number
PIC18C252-I/SP
Description
IC MCU OTP 16KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C252-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
23
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C252-I/SP
Manufacturer:
MAX
Quantity:
38
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 131 of 305
- Download datasheet (6Mb)
14.4.1.1
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘1111 0
A9 A8 0’, where A9 and A8 are the two MSbs of the
address. The sequence of events for 10-bit address is
as follows, with steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2001 Microchip Technology Inc.
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit BF is set.
An ACK pulse is generated.
MSSP interrupt flag bit SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Addressing
14.4.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
14.4.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 14-9).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Pin RC3/SCK/SCL should be enabled by setting bit
CKP.
Reception
Transmission
PIC18CXX2
DS39026C-page 129
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