PIC18C252-I/SP Microchip Technology, PIC18C252-I/SP Datasheet - Page 136
![IC MCU OTP 16KX16 A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18C252-I/SP
Manufacturer Part Number
PIC18C252-I/SP
Description
IC MCU OTP 16KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C252-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
23
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C252-I/SP
Manufacturer:
MAX
Quantity:
38
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 136 of 305
- Download datasheet (6Mb)
PIC18CXX2
14.4.4
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1.
2.
3.
4.
5.
6.
FIGURE 14-13:
DS39026C-page 134
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
SDA
SCL
I
2
C MASTER MODE SUPPORT
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
SDA in
Bus Collision
SCL in
Read
MSb
Write Collision Detect
START bit, STOP bit,
START bit Detect
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
SSPSR
Generate
2
C MASTER MODE)
LSb
Write
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2001 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
2
C
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