PIC18C252-I/SP Microchip Technology, PIC18C252-I/SP Datasheet - Page 83
![IC MCU OTP 16KX16 A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18C252-I/SP
Manufacturer Part Number
PIC18C252-I/SP
Description
IC MCU OTP 16KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C252-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
23
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C252-I/SP
Manufacturer:
MAX
Quantity:
38
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 83 of 305
- Download datasheet (6Mb)
FIGURE 8-5:
FIGURE 8-6:
2001 Microchip Technology Inc.
Note 1: I/O pins have diode protection to V
Note 1: I/O pin has diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register.
CCP Output
CCP2 Input
Enable
CCP Output
WR TRISB
RD PORTB
Data Bus
WR LATB or
WR PORTB
RBPU
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3
(2)
CCP2MX
(3)
(3)
Data Bus
WR TRIS
WR Port
RB0/INT
RBPU
(3)
(2)
Schmitt Trigger
Buffer
RD TRISB
RD LATB
RD PORTB
TRIS Latch
Data Latch
D
D
CK
CK
DD
DD
and V
and V
Q
Q
RD TRIS
RD Port
TRIS Latch
Data Latch
CCP2MX = 0
D
D
CK
CK
SS
Schmitt Trigger Buffer
SS
.
.
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
V
N
P
SS
DD
I/O pin
TTL
Input
Buffer
(1)
V
P
DD
PIC18CXX2
Weak
Pull-up
I/O pin
(1)
DS39026C-page 81
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