PIC16C72-20I/SP Microchip Technology, PIC16C72-20I/SP Datasheet - Page 215

• Manufacturer Part Number: PIC16C72-20I/SP
• Description: IC MCU OTP 2KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-20I/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 19-11: I
TABLE 19-10: I
Parameter
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
1997 Microchip Technology Inc.
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast-mode (400 kHz) I
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
tsu;DAT
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
released.
SDA
Out
SDA
In
SCL
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
T
T
T
T
T
Note: Refer to Figure 19-1 for load conditions
T
T
HD
HD
SU
SU
SU
T
Sym
T
HIGH
LOW
T
Cb
T
BUF
AA
:
:
:
:
:
R
F
STO
STA
STA
DAT
DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
2
2
C BUS DATA TIMING
C BUS DATA REQUIREMENTS
Characteristic
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
90
103
91
2
C-bus device can be used in a standard-mode (100 kHz) I
109
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
20 + 0.1Cb
20 + 0.1Cb
Applicable Devices 72 73 73A 74 74A 76 77
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
107
CY
CY
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
2
Units
C-bus system, but the requirement
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
92
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
PIC16C7X
102
110
DS30390E-page 215
Conditions