ATMEGA32-16MU Atmel, ATMEGA32-16MU Datasheet - Page 344

• Manufacturer Part Number: ATMEGA32-16MU
• Description: IC AVR MCU 32K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2503Q–AVR–02/11
JTAG Interface and On-chip Debug System 219
IEEE 1149.1 (JTAG) Boundary-scan 225
Boot Loader Support – Read-While-Write Self-Programming 244
Memory Programming 256
Electrical Characteristics 287
ADC Noise Canceler 208
ADC Conversion Result 213
Features 219
Overview 219
Test Access Port – TAP 219
TAP Controller 221
Using the Boundary-scan Chain 222
Using the On-chip Debug System 222
On-chip Debug Specific JTAG Instructions 223
On-chip Debug Related Register in I/O Memory 224
Using the JTAG Programming Capabilities 224
Bibliography 224
Features 225
System Overview 225
Data Registers 225
Boundary-scan Specific JTAG Instructions 227
Boundary-scan Chain 229
ATmega32 Boundary-scan Order 239
Boundary-scan Description Language Files 243
Features 244
Application and Boot Loader Flash Sections 244
Read-While-Write and no Read-While-Write Flash Sections 244
Boot Loader Lock Bits 246
Entering the Boot Loader Program 247
Addressing the Flash during Self-Programming 249
Self-Programming the Flash 250
Program And Data Memory Lock Bits 256
Fuse Bits 257
Signature Bytes 258
Calibration Byte 258
Page Size 258
Parallel Programming Parameters, Pin Mapping, and Commands 259
Parallel Programming 261
SPI Serial Downloading 270
SPI Serial Programming Pin Mapping 270
Programming via the JTAG Interface 274
ATmega32(L)
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