ATMEGA32-16PU Atmel, ATMEGA32-16PU Datasheet
ATMEGA32-16PU
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ATMEGA32-16PU Summary of contents
Page 1
... ATmega32 • Speed Grades – MHz for ATmega32L – MHz for ATmega32 • Power Consumption at 1 MHz, 3V, 25°C for ATmega32L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® 8-bit Microcontroller 8-bit ...
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... Pin Configurations ATmega32(L) 2 Figure 1. Pinout ATmega32 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 (MOSI) PB5 ...
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... Overview Block Diagram 2503G–AVR–11/04 The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega32 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32 as listed on page 55. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... AVR CPU Core Introduction Architectural Overview ATmega32(L) 6 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR MCU Architecture ...
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... The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description. ATmega32(L) 7 ...
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... Status Register ATmega32(L) 8 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code ...
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... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. ATmega32(L) 0 Addr. R0 ...
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... The X-register, Y-register and Z-register Stack Pointer ATmega32(L) 10 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. ...
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... Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 42. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 ATmega32(L) , directly generated from the selected clock CPU ...
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... ATmega32(L) 12 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 42 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST fuse, see “ ...
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... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega32(L) 13 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32 Program Counter (PC bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of inter- nal data SRAM in the ATmega32 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 9. ...
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... Data RD Memory Access Instruction The ATmega32 contains 1024 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. “ ...
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... X X • Bits 15..10 – Res: Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bits 9..0 – EEAR9..0: EEPROM Address The EEPROM Address Registers in the 1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023 ...
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... ATmega32(L) 18 When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM ...
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... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega32(L) 19 ...
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... EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption ATmega32(L) 20 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ...
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... The I/O space definition of the ATmega32 is shown in “Register Summary” on page 325. All ATmega32 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space ...
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... I/O Clock – clk I/O Flash Clock – clk FLASH ATmega32(L) 22 Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...
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... The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is therefore the 1 MHz Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel Programmer. ATmega32(L) (1) Typ Time-out (V = 3.0V) ...
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... Crystal Oscillator ATmega32(L) 24 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two dif- ferent Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-to-rail swing on the output ...
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... These options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. ATmega32(L) Additional Delay from Reset ( ...
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... Low-frequency Crystal Oscillator External RC Oscillator ATmega32( use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors ...
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... Byte” on page 256. Table 9. Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 (1) 0001 0010 0011 0100 Note: 1. The device is shipped with this option selected. ATmega32(L) Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 Additional Delay from Reset (V = 5.0V) ...
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... Oscillator Calibration Register – OSCCAL ATmega32(L) 28 When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC). Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 ...
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... For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. ATmega32(L) Additional Delay from Reset ( ...
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... If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 22 presents the different clock systems in the ATmega32, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. ...
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... Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec- ommended instead of Power-save mode because the contents of the registers in the ATmega32(L) and clk , while allowing the other CPU ...
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... Standby Mode Extended Standby Mode Minimizing Power Consumption Analog to Digital Converter ATmega32(L) 32 Asynchronous Timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk chronous modules, including Timer/Counter2 if clocked asynchronously. When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode ...
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... Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega32(L) ) and the ADC clock (clk ) are stopped, the I/O ...
Page 34
... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 23. The ATmega32 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
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... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega32L and BODLEVEL = 0 for ATmega32. BODLEVEL = 1 is not applicable for ATmega32. ATmega32(L) ...
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... Power-on Reset ATmega32( Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15. The POR is activated whenever V detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach- ...
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... MCU after the Time-out period t Figure 18. External Reset During Operation CC ATmega32 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...
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... Watchdog Reset MCU Control and Status Register – MCUCSR ATmega32(L) 38 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t . Refer to page 39 for details on operation of the Watchdog Timer. ...
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... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega32 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 38. ...
Page 40
... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example void WDT_off(void reset WDT */ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } ATmega32(L) 41 ...
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... Interrupts Interrupt Vectors in ATmega32 ATmega32(L) 42 This section describes the specifics of the interrupt handling as performed in ATmega32. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11. Table 18. Reset and Interrupt Vectors Program (2) Vector No. Address Source (1) 1 $000 RESET ...
Page 43
... Note: 1. The Boot Reset Address is shown in Table 99 on page 253. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32 is: Address Labels Code ...
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... ATmega32(L) 44 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...
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... Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 242 for details on Boot Lock bits. ATmega32( ...
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... ATmega32(L) 46 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ...
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... Port Functions” on page 52. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega32( Logic See Figure 23 " ...
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... Ports as General Digital I/O Configuring the Pin ATmega32(L) 48 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 23. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk ...
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... The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low clocked into the PINxn Register at the ATmega32(L) I/O Pull-up ...
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... ATmega32(L) 50 succeeding positive clock edge. As indicated by the two arrows t single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock ...
Page 51
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the External Interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega32(L) / ...
Page 52
... Unconnected pins Alternate Port Functions ATmega32( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega32(L) Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...
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... Special Function I/O Register – SFIOR Alternate Functions of Port A ATmega32(L) 54 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “ ...
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... Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB6 bit. ATmega32(L) PA2/ADC2 PA1/ADC1 0 ...
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... ATmega32(L) 56 • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB5 bit. • ...
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... OC0 0 DIEOE 0 INT2 ENABLE DIEOV – INT2 INPUT AIO AIN1 INPUT AIN0 INPUT ATmega32(L) PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR 0 SPI MSTR OUTPUT ...
Page 58
... Alternate Functions of Port C ATmega32(L) 58 The Port C pins with alternate functions are shown in Table 28. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti- vated even if a reset occurs. Table 28. Port C Pins Alternate Functions Port Pin Alternate Function ...
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... DDOE AS2 AS2 DDOV 0 0 PVOE 0 0 PVOV 0 0 DIEOE AS2 AS2 DIEOV – – AIO T/C2 OSC OUTPUT T/C2 OSC INPUT ATmega32(L) PC5/TDI PC4/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI – 59 ...
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... Alternate Functions of Port D ATmega32(L) 60 Table 30. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/TMS PC2/TCK PUOE JTAGEN JTAGEN PUOV 1 1 DDOE JTAGEN JTAGEN DDOV 0 0 PVOE 0 0 PVOV 0 0 DIEOE JTAGEN JTAGEN DIEOV – – AIO TMS TCK Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1 ...
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... Figure 26 on page 52. Table 32. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/OC2 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC2 ENABLE PVOV OC2 DIEOE 0 DIEOV 0 DI – AIO – ATmega32(L) PD6/ICP1 PD5/OC1A OC1A ENABLE 0 OC1A ICP1 INPUT – – – PD4/OC1B ...
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... Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB ATmega32(L) 62 Table 33. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3/INT1 PUOE 0 PUOV ...
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... R/W R/W R/W Initial Value Bit DDD7 DDD6 DDD5 Read/Write R/W R/W R/W Initial Value Bit PIND7 PIND6 PIND5 Read/Write Initial Value N/A N/A N/A ATmega32( PINB4 PINB3 PINB2 PINB1 N/A N/A N/A N PORTC4 PORTC3 PORTC2 PORTC1 R/W R/W R/W R DDC4 ...
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... External Interrupts MCU Control Register – MCUCR ATmega32(L) 64 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register – ...
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... Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ATmega32( JTRF WDRF ...
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... General Interrupt Flag Register – GIFR ATmega32(L) 66 ISC10) in the MCU General Control Register (MCUCR) define whether the External Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 inter- rupt Vector ...
Page 67
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega32” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 68
... Definitions Timer/Counter Clock Sources Counter Unit ATmega32(L) 68 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the wave- form generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 69. for details. The compare match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request ...
Page 69
... Figure 29 shows a block diagram of the output compare unit. Figure 29. Output Compare Unit, Block Diagram OCRn = top bottom Waveform Generator FOCn WGMn1:0 ATmega32(L) ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn (8-bit Comparator ) COMn1:0 OCFn (Int ...
Page 70
... Using the Output Compare Unit Compare Match Output Unit ATmega32(L) 70 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence ...
Page 71
... PWM). For non-PWM modes the COM01:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 70.). For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in “Timer/Counter Timing Diagrams” on page 76. ATmega32( OCn ...
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... Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega32(L) 72 The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00) ...
Page 73
... Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM01 (See Table 40 on page 79). The actual OC0 value will only be visible on the port pin if the data direction for the port ATmega32(L) f clk_I/O ...
Page 74
... Phase Correct PWM Mode ATmega32(L) 74 pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0 Register at the compare match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). ...
Page 75
... OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. ATmega32(L) OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set ...
Page 76
... Timer/Counter Timing Diagrams ATmega32(L) 76 • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures ...
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... Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn ATmega32(L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 77 ...
Page 78
... Timer/Counter Register Description Timer/Counter Control Register – TCCR0 ATmega32(L) 78 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode ...
Page 79
... Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 42. Clock Select Bit Description CS02 CS01 CS00 Description clock source (Timer/Counter stopped). clk I/O clk I/O ATmega32(L) (1) (1) /(No prescaling) /8 (From prescaler) 79 ...
Page 80
... Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK ATmega32(L) 80 Table 42. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description clk /64 (From prescaler) I/O clk /256 (From prescaler) I/O clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge. ...
Page 81
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. ATmega32( ...
Page 82
... Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega32(L) 82 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2 ...
Page 83
... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega32(L) < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O /2 ...
Page 84
... Timer/Counter1 Overview ATmega32(L) 84 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two Independent Output Compare Units • ...
Page 85
... T The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin ATmega32(L) (1) TOVn (Int.Req.) Control Logic ...
Page 86
... Definitions Compatibility ATmega32(L) 86 (OC1A/B). See “Output Compare Units” on page 92. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output com- pare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1 the Analog Compar- ator pins (See “ ...
Page 87
... Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. ATmega32(L) 87 ...
Page 88
... ATmega32(L) 88 The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 ...
Page 89
... Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 82. The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 41 shows a block diagram of the counter and its surroundings. ATmega32(L) 89 ...
Page 90
... ATmega32(L) 90 Figure 41. Counter Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clk Timer/Counter clock ...
Page 91
... Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be writ- ten to the ICR1H I/O location before the low byte is written to ICR1L. ATmega32(L) DATA BUS (8-bit) ...
Page 92
... Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units ATmega32(L) 92 For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 87. The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). ...
Page 93
... Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high ATmega32(L) DATA BUS (8-bit) ...
Page 94
... Using the Output Compare Unit Compare Match Output Unit ATmega32(L) 94 byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Reg- ister in the same system clock cycle. For more information of how to access the 16-bit registers refer to “ ...
Page 95
... PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the out- put should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 94.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 103. ATmega32( OCnx ...
Page 96
... Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega32(L) 96 The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000) ...
Page 97
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com- pare match occurs. ATmega32( when OCR1A is set to zero (0x0000). The 1 ...
Page 98
... ATmega32(L) 98 Figure 46. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com- pare values ...
Page 99
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATmega32(L) f clk_I/O = ---------------------------------- - ⋅ ...
Page 100
... ATmega32(L) 100 Figure 47. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP) ...
Page 101
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com- pare match occurs. ATmega32(L) f clk_I/O = --------------------------- - ⋅ ...
Page 102
... ATmega32(L) 102 Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 2 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP ...
Page 103
... Figure 50 shows the same timing data, but with the prescaler enabled. Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATmega32(L) T1 OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value ) is therefore OCRnx + 2 /8) clk_I/O OCRnx + 2 ...
Page 104
... ATmega32(L) 104 Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM ...
Page 105
... WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 44. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. ATmega32( COM1B0 FOC1A FOC1B WGM11 R R/W 0 ...
Page 106
... ATmega32(L) 106 Table 45. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 97. for more details. ...
Page 107
... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega32(L) Update of TOV1 Flag Set x TOP OCR1 on 0xFFFF Immediate MAX 0x00FF TOP BOTTOM 0x01FF TOP BOTTOM 0x03FF TOP BOTTOM ...
Page 108
... Timer/Counter1 Control Register B – TCCR1B ATmega32(L) 108 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output ...
Page 109
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 87. ATmega32( ...
Page 110
... Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega32(L) 110 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value ...
Page 111
... TOV1 Flag is set when the timer overflows. Refer to Table 47 on page 107 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega32( ...
Page 112
... Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega32” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 113
... Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 ATmega32( default equal to the MCU clock, clk T2 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top . ...
Page 114
... Output Compare Unit ATmega32(L) 114 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T2 clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped ...
Page 115
... Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. ATmega32(L) 115 ...
Page 116
... Compare Output Mode and Waveform Generation Modes of Operation ATmega32(L) 116 Figure 56. Compare Match Output Unit, Schematic COMn1 Waveform COMn0 Generator FOCn clk I/O The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direc- tion (input or output) is still controlled by the Data Direction Register (DDR) for the port pin ...
Page 117
... Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum fre- ATmega32(L) OCn Interrupt Flag Set 2 ...
Page 118
... Fast PWM Mode ATmega32(L) 118 quency when OCR2 is set to zero (0x00). The waveform frequency is OC2 clk_I/O defined by the following equation: f OCn The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the that the counter counts from MAX to 0x00. ...
Page 119
... Figure 59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. ATmega32(L) f clk_I/O f ...
Page 120
... ATmega32(L) 120 Figure 59. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag ( TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin ...
Page 121
... Figure 61 shows the same timing data, but with the prescaler enabled. Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. ATmega32(L) MAX BOTTOM /8) clk_I/O MAX BOTTOM should I/O BOTTOM + 1 BOTTOM + 1 121 ...
Page 122
... ATmega32(L) 122 Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f ...
Page 123
... These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to OC2 pin must be set in order to enable the output driver. ATmega32( ...
Page 124
... ATmega32(L) 124 When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 51. Compare Output Mode, non-PWM Mode COM21 ...
Page 125
... Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt generate a waveform output on the OC2 pin. ATmega32(L) Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) ...
Page 126
... Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 ATmega32(L) 126 Bit – – – Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk AS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin ...
Page 127
... Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up ATmega32(L) 127 ...
Page 128
... Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega32(L) 128 from Power-save mode, and the I/O clock (clk read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time ...
Page 129
... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega32(L) 10-BIT T/C PRESCALER Clear 0 ...
Page 130
... Serial Peripheral Interface – SPI ATmega32(L) 130 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32 and peripheral devices or between several AVR devices. The ATmega32 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 131
... MOSI User Defined MISO Input SCK User Defined SS User Defined Note: See “Alternate Functions of Port B” on page 55 for a detailed description of how to define the direction of the user defined SPI pins. ATmega32(L) MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK SS ...
Page 132
... ATmega32(L) 132 The following code examples show how to initialize the SPI as a master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB ...
Page 133
... SPI_SlaveInit(void Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; } Note: 1. See “About Code Examples” on page 5. ATmega32(L) 133 ...
Page 134
... SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega32(L) 134 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...
Page 135
... SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 58. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega32(L) Trailing Edge Trailing Edge Setup SPR0 SCK Frequency osc osc osc f / ...
Page 136
... CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran- teed to work lower. osc The SPI interface on the ATmega32 is also used for program memory and EEPROM downloading or uploading. See page 268 for SPI Serial Programming and Verification. Bit 7 ...
Page 137
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB ATmega32(L) Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 138
... USART Overview ATmega32(L) 138 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • ...
Page 139
... U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 70 shows a block diagram of the clock generation logic. ATmega32(L) 139 ...
Page 140
... Internal Clock Generation – The Baud Rate Generator ATmega32(L) 140 Figure 70. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). ...
Page 141
... The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. ATmega32(L) Equation for Equation for Calculating Calculating UBRR ...
Page 142
... Frame Formats ATmega32(L) 142 Figure 71. Synchronous Mode XCK Timing. UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 71 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge ...
Page 143
... Parity bit using even parity even P Parity bit using odd parity odd d Data bit n of the character n If used, the parity bit is located between the last data bit and first stop bit of a serial frame. ATmega32(L) ⊕ … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 144
... USART Initialization ATmega32(L) 144 The USART has to be initialized before any communication can take place. The initial- ization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization ...
Page 145
... See “About Code Examples” on page 5. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega32(L) 145 ...
Page 146
... Sending Frames with 9 Data Bit Transmitter Flags and Interrupts ATmega32(L) 146 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16 ...
Page 147
... The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD pin. ATmega32(L) 147 ...
Page 148
... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega32(L) 148 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input ...
Page 149
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: 1. See “About Code Examples” on page 5. ATmega32(L) 149 ...
Page 150
... Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker ATmega32(L) 150 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ...
Page 151
... Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). ATmega32(L) 151 ...
Page 152
... Asynchronous Data Recovery ATmega32(L) 152 Figure 73. Start Bit Sampling RxD IDLE Sample (U2X = Sample (U2X = When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam- ple as shown in the figure ...
Page 153
... Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the slow receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. ATmega32(L) STOP 1 (A) ( 0/1 ...
Page 154
... ATmega32(L) 154 Table 61 and Table 62 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) ...
Page 155
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega32(L) 155 ...
Page 156
... Accessing UBRRH/ UCSRC Registers Write Access ATmega32(L) 156 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written ...
Page 157
... Data Buffer Register (TXB) will be the destination for data written to the UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. ATmega32( ...
Page 158
... USART Control and Status Register A – UCSRA ATmega32(L) 158 The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the transmit Shift Register when the Shift Register is empty ...
Page 159
... Writing this bit to one enables the USART Transmitter. The Transmitter will override nor- mal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmis- sions are completed, i.e., when the transmit Shift Register and transmit Buffer Register ATmega32( ...
Page 160
... USART Control and Status Register C – UCSRC ATmega32(L) 160 do not contain data to be transmitted. When disabled, the transmitter will no longer over- ride the TxD port. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size frame the receiver and transmitter use. • ...
Page 161
... The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size frame the Receiver and Transmitter use. Table 66. UCSZ Bits Settings UCSZ2 UCSZ1 ATmega32(L) Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity Stop Bit(s) 1-bit 2-bit UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved ...
Page 162
... USART Baud Rate Registers – UBRRL and UBRRH ATmega32(L) 162 • Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK) ...
Page 163
... ATmega32(L) BaudRate ⎛ ⎞ Closest Match • ------------------------------------------------------- - 1 100% – ⎝ ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0. ...
Page 164
... Max 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATmega32(L) 164 f = 4.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...
Page 165
... Mbps 691.2 kbps ATmega32(L) MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0. ...
Page 166
... Max 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega32(L) 166 f = 18.4320 MHz osc U2X = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% ...
Page 167
... Description Master The device that initiates and terminates a transmission. The master also generates the SCL clock. Slave The device addressed by a master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. ATmega32( Device 3 ........ Device 167 ...
Page 168
... Data Transfer and Frame Format Transferring Bits START and STOP Conditions ATmega32(L) 168 As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the opera- tion of the interface ...
Page 169
... An Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is sig- nalled. When the receiver has received the last byte, or for some reason cannot receive ATmega32(L) STOP START REPEATED START ...
Page 170
... Combining Address and Data Packets into a Transmission Multi-master Bus Systems, Arbitration and Synchronization ATmega32(L) 170 any more bytes, it should inform the transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 80. Data Packet Format Data MSB ...
Page 171
... Arbitration will continue until only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration will continue into the data packet. ATmega32(L) TA low ...
Page 172
... ATmega32(L) 172 Figure 83. Arbitration between Two Masters START SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’ ...
Page 173
... SDA and SCL for the reminder of the byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA + R slave (a slave does not need to be connected to the bus for the condition to happen). ATmega32(L) SDA Slew-rate Spike ...
Page 174
... Bus Interface Unit Address Match Unit Control Unit ATmega32(L) 174 This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con- troller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received ...
Page 175
... Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a ATmega32( ...
Page 176
... TWI Status Register – TWSR ATmega32(L) 176 START condition on the bus free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • ...
Page 177
... If a match is found, an interrupt request is generated. • Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. ATmega32(L) Prescaler Value ...
Page 178
... TWI Status code indicates Hardware START condition sent Action ATmega32(L) 178 • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition ...
Page 179
... TWI bus cycle example, TWDR must be loaded with the value to be transmitted in the next bus cycle. • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be ATmega32(L) 179 ...
Page 180
... TWCR, r16 ATmega32(L) 180 set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files ...
Page 181
... The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. ATmega32(L) 181 ...
Page 182
... ATmega32(L) 182 Figure 86. Data Transfer in Master Transmitter Mode Device 1 Device 2 MASTER SLAVE TRANSMITTER RECEIVER SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag ...
Page 183
... No TWDR action TWDR action TWDR action TWDR action TWDR action 1 0 ATmega32(L) TWINT TWEA Next Action Taken by TWI Hardware 1 X SLA+W will be transmitted; ACK or NOT ACK will be received 1 X SLA+W will be transmitted; ACK or NOT ACK will be received 1 X SLA+R will be transmitted; ...
Page 184
... Master Receiver Mode ATmega32(L) 184 Figure 87. Formats and States in the Master Transmitter Mode MT Successfull S SLA W transmission to a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave ...
Page 185
... After a repeated START condition (state $10) the Two-wire Serial Interface can access the same slave again new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. ATmega32( Device 3 ...
Page 186
... SLA+R has been transmitted; NOT ACK has been received $50 Data byte has been received; ACK has been returned $58 Data byte has been received; NOT ACK has been returned ATmega32(L) 186 Application Software Response To TWCR To/from TWDR STA STO TWINT Load SLA+R ...
Page 187
... Figure 90. Data Transfer in Slave Receiver Mode Device 1 Device 2 SLAVE MASTER RECEIVER TRANSMITTER SDA SCL To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value ATmega32(L) DATA A DATA A $50 $58 P Other master Other master A continues continues $38 Other master ...
Page 188
... ATmega32(L) 188 The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR TWINT TWEA ...
Page 189
... ATmega32(L) TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...
Page 190
... Slave Transmitter Mode ATmega32(L) 190 Figure 91. Formats and States in the Slave Receiver Mode Reception of the own S SLA W slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call ...
Page 191
... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega32(L) TWSTA TWSTO TWWC ...
Page 192
... ACK has been received $C0 Data byte in TWDR has been transmitted; NOT ACK has been received $C8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATmega32(L) 192 Application Software Response To TWCR To/from TWDR STA STO TWINT Load data byte or X ...
Page 193
... TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Application Software Response To TWCR To/from TWDR STA STO No TWDR action No TWCR action No TWDR action 0 1 ATmega32(L) A DATA A DATA $A8 $B8 A $B0 Any number of data bytes A and their associated acknowledge bits ...
Page 194
... Combining Several TWI Modes Multi-master Systems and Arbitration ATmega32(L) 194 In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2 ...
Page 195
... No Address / General Call received Yes Write Direction Read ATmega32(L) Data Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free 68/78 Data byte will be received and NOT ACK will be returned ...
Page 196
... Analog Comparator Special Function IO Register – SFIOR ATmega32(L) 196 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function ...
Page 197
... Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter- rupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set. ATmega32( ...
Page 198
... Analog Comparator Multiplexed Input ATmega32(L) 198 • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter- rupt. The different settings are shown in Table 79. Table 79. ACIS1/ACIS0 Settings ACIS1 ACIS0 ...
Page 199
... The differential input channels are not tested for devices in PDIP Package. This fea- ture is only guaranteed to work for devices in TQFP and MLF Packages The ATmega32 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A ...
Page 200
... Operation ATmega32(L) 200 Figure 98. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL 2.56V REFERENCE AREF GND BANDGAP REFERENCE ADC7 ADC6 POS. ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX The ADC converts an analog input voltage to a 10-bit digital value through successive approximation ...