PIC18F4220-I/ML Microchip Technology, PIC18F4220-I/ML Datasheet - Page 190
![IC MCU FLASH 2KX16 EEPROM 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4220-I/ML
Manufacturer Part Number
PIC18F4220-I/ML
Description
IC MCU FLASH 2KX16 EEPROM 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F1320-ISS PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- Current page: 190 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
17.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
the SCL pin is deasserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for T
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
FIGURE 17-24:
DS39599G-page 188
ACKNOWLEDGE SEQUENCE TIMING
WCOL Status Flag
Note: T
Sequence
Note: T
SSPIF
SCL
SDA
Acknowledge sequence starts here,
SDA
SCL
Write to SSPCON2,
Falling edge of
9th clock
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
BRG
Set SSPIF at the end
of receive
. The SCL pin is then pulled
= one Baud Rate Generator period.
ACK
= one Baud Rate Generator period.
ACKEN = 1, ACKDT = 0
Enable
set PEN
write to SSPCON2,
bit,
8
D0
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
BRG
ACKEN
) and
T
SCL brought high after T
BRG
Cleared in
software
T
BRG
P
ACK
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 17-24).
17.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
(Baud Rate Generator rollover count) later, the
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
STOP CONDITION TIMING
, followed by SDA = 1 for T
later, the PEN bit is cleared and the SSPIF
WCOL Status Flag
ACKEN automatically cleared
© 2007 Microchip Technology Inc.
Cleared in software
BRG
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