PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 4

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GB110 FAMILY
6. Module: SPI (Master Mode)
7. Module: CTMU
EXAMPLE 1:
DS80369K-page 4
In Master mode, both the SPI Interrupt Flag
(SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled (SPIBEN = 0)
• The module is configured for serial data output
If the application is using the interrupt flag to deter-
mine when data to be transmitted is written to the
transmit buffer, the data currently in the buffer may
be overwritten.
Work around
Before writing to the SPI buffer, check the SCK pin
to determine if the last clock edge has passed.
Example 1
doing this. In this example, pin, RD1, functions as
the SPI clock, SCK, which is configured as Idle low.
Affected Silicon Revisions
When the CTMU module is selected as the trigger
source (SYNCSEL<4:0> = 11000), the output
compare or input capture module triggers may not
work.
Work around
Manually trigger the output compare and/or input
capture modules after a CTMU event is received.
Be certain to compensate for any time latency
required by manually triggering the module.
Affected Silicon Revisions
while(IFS0bits.SPI1IF == 0){}
while(PORTDbits.RD1 == 1){}
SPI1BUF = 0xFF;
A3
A3
changes on transition from clock active to clock
Idle state (CKE = 1)
X
X
A5
A5
(below) demonstrates a method for
CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK
//wait for the transmission to complete
//wait for the last clock to finish
//write new data to the buffer
8. Module: USB
9. Module: USB (V
10. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the PRE signal may not be generated correctly.
This will result in not being able to communicate
correctly with the low-speed device.
Work around
Connect low-speed devices directly to the
application and not through a USB hub.
Affected Silicon Revisions
The USB internal voltage regulator does not
regulate to 3.3V. The USB internal voltage regulator
is an optional feature and is not required for USB
operation or compliance.
Work around
Disable the USB voltage regulator (DISUVREG
Configuration bit set to ‘1’) and supply 3.0V to 3.6V
from an external source to the V
Affected Silicon Revisions
When the module is configured to use an external
transceiver, the CRC5 value of some packets may
be incorrect.
Work around
Use the module’s internal transceiver.
Affected Silicon Revisions
A3
A3
A3
X
X
X
A5
A5
A5
X
X
X
USB
 2010 Microchip Technology Inc.
Regulator)
USB
pin.