PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet
PIC24FJ256GB110-I/PF
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PIC24FJ256GB110-I/PF Summary of contents
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... PIC24FJ256GB110 Family © 2008 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Preliminary DS39897B ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC24FJ256GB110 100 256K 16K © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY High-Performance CPU: • Modified Harvard Architecture • MIPS Operation at 32 MHz • 8 MHz Internal Oscillator • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16-Bit Working Register Array • ...
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... PIC24FJ256GB110 FAMILY Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer 2 • ...
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... PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 PGEC3/RP18/V /C1INA/AN5/CN7/RB5 BUSON PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/V -/AN1/CN3/RB1 REF PGED1/RP0/PMA6/V +/AN0/CN2/RB0 REF Legend: RPn represents remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJXXXGB106 Preliminary RPI37/SOSCO/C3INC/TICK/ 48 CN0/RC14 47 SOSCI/C3IND/CN1/RC13 ...
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... PIC24FJ256GB110 FAMILY Pin Diagram (80-Pin TQFP) 1 PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 2 PMD7/SDA3/CN65/RE7 3 RPI38/CN45/RC1 4 RPI40/CN47/RC3 5 PMA5/RP21/C1IND/CN8/RG6 6 RP26/PMA4/C1INC/CN9/RG7 7 PMA3/RP19/C2IND/CN10/RG8 8 MCLR 9 RP27/PMA2/C2INC/CN11/RG9 TMS/RPI33/CN66/RE8 13 TDO/RPI34/CN67/RE9 14 PGEC3/RP18/V /C1INA/AN5/CN7/RB5 BUSON 15 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 16 VPIO/C2INA/AN3/CN5/RB3 17 VMIO/RP13/C2INB/AN2/CN4/RB2 18 PGEC1/RP1/AN1/CN3/RB1 19 PGED1/RP0/AN0/CN2/RB0 20 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. DS39897B-page PIC24FJXXXGB108 50 49 ...
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... TMS/CN33/RA0 17 RPI33/CN66/RE8 18 RPI34/CN67/RE9 19 PGEC3/RP18/V /C1INA/AN5/CN7/RB5 BUSON 20 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 21 VPIO/C2INA/AN3/CN5/RB3 22 VMIO/RP13/C2INB/AN2/CN4/RB2 23 PGEC1/RP1/AN1/CN3/RB1 24 PGED1/RP0/AN0/CN2/RB0 25 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJXXXGB110 Preliminary RPI37/SOSCO/C3INC/T1CK/ 74 CN0/RC14 73 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 72 RP12/PMCS1/CN56/RD11 71 RP3/PMCS2/CN55/RD10 70 RP4/DPLN/CN54/RD9 69 RP2/DMLN/RTCC/CN53/RD8 68 RPI35/SDA1/CN44/RA15 67 ...
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... PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU ........................................................................................................................................................................................... 25 3.0 Memory Organization ................................................................................................................................................................. 31 4.0 Flash Program Memory .............................................................................................................................................................. 55 5.0 Resets ........................................................................................................................................................................................ 61 6.0 Interrupt Controller ..................................................................................................................................................................... 67 7.0 Oscillator Configuration ............................................................................................................................................................ 109 8.0 Power-Saving Features ............................................................................................................................................................ 119 9.0 I/O Ports ................................................................................................................................................................................... 121 10.0 Timer1 ...................................................................................................................................................................................... 147 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 149 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 7 ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 8 Preliminary © 2008 Microchip Technology Inc. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...
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... Details on Individual Family Members Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in four ways: 1 ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
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... PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
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... TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
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... PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control OSCO/CLKO OSCI/CLKI Power-up Timing Timer Generation Oscillator Start-up Timer FRC/LPRC ...
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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin 80-Pin TQFP TQFP AN0 16 20 AN1 15 19 AN2 14 18 AN3 13 17 AN4 12 16 AN5 11 15 AN6 17 21 AN7 18 22 AN8 21 27 AN9 22 28 AN10 23 29 AN11 24 30 AN12 27 33 AN13 28 34 ...
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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP TQFP CN0 48 60 CN1 47 59 CN2 16 20 CN3 15 19 CN4 14 18 CN5 13 17 CN6 12 16 CN7 11 15 CN8 4 6 CN9 5 7 CN10 6 8 CN11 8 10 ...
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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP TQFP CN43 — 52 CN44 — 53 CN45 — 4 CN46 — — CN47 — 5 CN48 — — CN49 46 58 CN50 49 61 CN51 50 62 CN52 51 63 CN53 42 54 CN54 43 55 CN55 ...
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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP TQFP DMH 46 58 DMLN 42 54 DPH 50 62 DPLN 43 55 ENVREG 57 71 INT0 46 58 MCLR 7 9 OSCI 39 49 OSCO 40 50 PGEC1 15 19 PGED1 16 20 PGEC2 17 21 ...
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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP TQFP PMD0 60 76 PMD1 61 77 PMD2 62 78 PMD3 63 79 PMD4 64 80 PMD5 1 1 PMD6 2 2 PMD7 3 3 PMRD 53 67 PMWR 52 66 RA0 — — RA1 — — RA2 — ...
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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP TQFP RC1 — 4 RC2 — — RC3 — 5 RC4 — — RC12 39 49 RC13 47 59 RC14 48 60 RC15 40 50 RCV 18 22 RD0 46 58 RD1 49 61 ...
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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP TQFP RF0 58 72 RF1 59 73 RF2 — 42 RF3 33 41 RF4 31 39 RF5 32 40 RF8 — 43 RF12 — — RF13 — — RG0 — 75 RG1 — 74 RG2 37 47 RG3 ...
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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP TQFP RP20 53 67 RP21 4 6 RP22 51 63 RP23 50 62 RP24 49 61 RP25 52 66 RP26 5 7 RP27 8 10 RP28 12 16 RP29 30 36 RP30 — 42 RP31 — ...
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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP TQFP BUS BUSON BUSST CAP CMPST CMPST CPCON V 10, 26, 38 12, 32 16, 37 DDCORE VMIO 14 18 VPIO REF REF V 9, 25, 41 11, 31, 51 15, 36, 45 USB Legend: TTL = TTL input buffer ANA = Analog level input/output © ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 24 Preliminary © 2008 Microchip Technology Inc. ...
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... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... PIC24FJ256GB110 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...
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... W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
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... PIC24FJ256GB110 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ256GB110 FAMILY 2.3.2 DIVIDER The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
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... Program Address Space The program address memory PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES PIC24FJ64GB1XX PIC24FJ128GB1XX GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table ...
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... On device Reset, the config- uration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration PIC24FJ256GB110 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format ...
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... Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility”). FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES MSB Address 0001h 07FFh ...
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... PIC24FJ256GB110 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 35 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 36 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 37 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 38 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 39 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 40 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 41 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 42 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 43 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 44 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 45 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 46 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 47 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 48 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 49 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 50 Preliminary © 2008 Microchip Technology Inc. ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... PIC24FJ256GB110 FAMILY TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG< ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PIC24FJ256GB110 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i ...
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... JTAG • Enhanced In-Circuit Serial Programming™ (Enhanced ICSP™) ICSP allows a PIC24FJ256GB110 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx ...
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... PIC24FJ256GB110 FAMILY 4.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) U-0 U-0 — — (1) U-0 ...
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... PIC24FJ256GB110 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
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... PIC24FJ256GB110 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH ...
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... Illegal Opcode Configuration Mismatch Uninitialized W Register © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... PIC24FJ256GB110 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... PIC24FJ256GB110 FAMILY TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC, FRC, FRCDIV, LPRC T ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL MCLR Any Clock WDT Any Clock ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 66 Preliminary © 2008 Microchip Technology Inc. ...
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... These are summarized in Table 6-1 and Table 6-2. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... PIC24FJ256GB110 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...
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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah ...
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... UART4 Receiver UART4 Transmitter USB Interrupt 6.3 Interrupt Control and Status Registers The PIC24FJ256GB110 family of devices implements a total of 36 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS5 • IEC0 through IEC5 • IPC0 through IPC23 (except IPC14 and IPC17) Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
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... See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 — — ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF R/W-0 ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 (1) T5IE T4IE ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 “ ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE U-0 ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 R/W-0 R/W-0 (1) — INT4IE INT3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...
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... PIC24FJ256GB110 FAMILY REGISTER 6-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 — — IC9IE bit 15 R/W-0 R/W-0 R/W-0 U4ERIE USB1IE MI2C3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
Page 89
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — ...
Page 90
... PIC24FJ256GB110 FAMILY REGISTER 6-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP2 T2IP1 bit 15 U-0 R/W-1 R/W-0 — IC2IP2 IC2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — ...
Page 92
... PIC24FJ256GB110 FAMILY REGISTER 6-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP2 AD1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
Page 93
... SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — ...
Page 94
... PIC24FJ256GB110 FAMILY REGISTER 6-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP2 IC8IP1 bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 95
... OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — ...
Page 96
... PIC24FJ256GB110 FAMILY REGISTER 6-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 — INT2IP2 INT2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — ...
Page 98
... PIC24FJ256GB110 FAMILY REGISTER 6-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 — IC5IP2 IC5IP1 bit 15 U-0 R/W-1 R/W-0 — IC3IP2 IC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 99
... IC6IP2:IC6IP0: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 U-0 R/W-1 OC5IP0 — ...
Page 100
... PIC24FJ256GB110 FAMILY REGISTER 6-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PMPIP2 PMPIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
Page 101
... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 U-0 U-0 SI2C2P0 — ...
Page 102
... PIC24FJ256GB110 FAMILY REGISTER 6-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT3IP2 INT3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 103
... RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — ...
Page 104
... PIC24FJ256GB110 FAMILY REGISTER 6-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 — U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 105
... CTMUIP2:CTMUIP0: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 106
... PIC24FJ256GB110 FAMILY REGISTER 6-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 — U3TXIP2 U3TXIP1 bit 15 U-0 R/W-1 R/W-0 — U3ERIP2 U3ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 107
... SI2C3P2:SI2C3P0: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 U-0 R/W-1 MI2C3P0 — ...
Page 108
... PIC24FJ256GB110 FAMILY REGISTER 6-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 — SPI3IP2 SPI3IP1 bit 15 U-0 R/W-1 R/W-0 — U4TXIP2 U4TXIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 109
... OC9IP2:OC9IP0: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 IC9IP0 — ...
Page 110
... PIC24FJ256GB110 FAMILY 6.4 Interrupt Setup Procedures 6.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 111
... For more information, refer to the “PIC24F Family Reference ”Section 6. Oscillator” (DS39700). The oscillator system for PIC24FJ256GB110 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 7-1: PIC24FJ256GB110 FAMILY CLOCK DIAGRAM ...
Page 112
... PIC24FJ256GB110 FAMILY 7.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator ...
Page 113
... Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The OSCCON register (Register 7-1) is the main con- trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. ...
Page 114
... PIC24FJ256GB110 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...
Page 115
... Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...
Page 116
... PIC24FJ256GB110 FAMILY REGISTER 7-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 ...
Page 117
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. ...
Page 118
... USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ256GB110 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals ...
Page 119
... In addition to the CLKO output (F module in certain oscillator modes, the device clock in the PIC24FJ256GB110 family devices can also be config- ured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configura- tions and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
Page 120
... PIC24FJ256GB110 FAMILY REGISTER 7-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROEN — ROSSLP bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROEN: Reference Oscillator Output Enable bit ...
Page 121
... Family Reference ”Section 10. Power-Saving Features” (DS39698). The PIC24FJ256GB110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • ...
Page 122
... PIC24FJ256GB110 FAMILY 8.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 123
... Data Latch Read LAT Read PORT © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled ...
Page 124
... DS39897B-page 122 9.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB110 family of devices to gen- erate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. Depending ...
Page 125
... PIC24FJ256GB110 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are remappable input/output pins, depending on the pin count of the particular device selected ...
Page 126
... PIC24FJ256GB110 FAMILY 9.4.3.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 9-1 through Register 9-21) ...
Page 127
... IrDA BCLK functionality uses this output. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 9-2). Because of the mapping technique, the list of peripher- als for output mapping also includes a null value of ‘ ...
Page 128
... PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock TABLE 9-3: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GB110 FAMILY DEVICES Device Pin Count Total 64-pin 28 80-pin 31 ...
Page 129
... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that fea- ture on. The peripheral must be specifically configured for operation and enabled were tied to a fixed pin ...
Page 130
... PIC24FJ256GB110 FAMILY 9.4.6 PERIPHERAL PIN SELECT REGISTERS The PIC24FJ256GB110 family of devices implements a total of 37 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (21) • Output Remappable Peripheral Registers (16) REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 — ...
Page 131
... T3CKR5:T3CKR0: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR5:T2CKR0: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 T1CKR4 T1CKR3 ...
Page 132
... PIC24FJ256GB110 FAMILY REGISTER 9-5: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 — — T5CKR5 bit 15 U-0 U-0 R/W-1 — — T4CKR5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 133
... IC6R5:IC6R0: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R5:IC5R0: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC4R4 IC4R3 IC4R2 ...
Page 134
... PIC24FJ256GB110 FAMILY REGISTER 9-9: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 — — IC8R5 bit 15 U-0 U-0 R/W-1 — — IC7R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 135
... Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR5:U3RXR0: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC9R4 IC9R3 IC9R2 U-0 ...
Page 136
... PIC24FJ256GB110 FAMILY REGISTER 9-13: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 — — U1CTSR5 bit 15 U-0 U-0 R/W-1 — — U1RXR5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 137
... U3CTSR5:U3CTSR0: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R5:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 SCK1R4 SCK1R3 ...
Page 138
... PIC24FJ256GB110 FAMILY REGISTER 9-17: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 — — SCK2R5 bit 15 U-0 U-0 R/W-1 — — SDI2R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 139
... SCK3R5:SCK3R0: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R5:SDI3R0: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 U4CTSR4 U4CTSR3 ...
Page 140
... PIC24FJ256GB110 FAMILY REGISTER 9-21: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — SS3R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 141
... RP4R5:RP4R0: RP4 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP4 (see Table 9-2 for peripheral function numbers) Note 1: Unimplemented in 64-pin devices; read as ‘0’. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 RP3R4 RP3R3 RP3R2 ...
Page 142
... PIC24FJ256GB110 FAMILY REGISTER 9-25: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 — — RP7R5 bit 15 U-0 U-0 R/W-0 — — RP6R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 143
... Unimplemented: Read as ‘0’ bit 5-0 RP12R5:RP12R0: RP12 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP12 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP11R4 RP11R3 RP11R2 ...
Page 144
... PIC24FJ256GB110 FAMILY REGISTER 9-29: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 — — RP15R5 bit 15 U-0 U-0 R/W-0 — — RP14R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 145
... Unimplemented: Read as ‘0’ bit 5-0 RP20R5:RP20R0: RP20 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP20 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP19R4 RP19R3 RP19R2 ...
Page 146
... PIC24FJ256GB110 FAMILY REGISTER 9-33: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 — — RP23R5 bit 15 U-0 U-0 R/W-0 — — RP22R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 147
... Unimplemented: Read as ‘0’ bit 5-0 RP28R5:RP28R0: RP28 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP28 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP27R4 RP27R3 RP27R2 ...
Page 148
... PIC24FJ256GB110 FAMILY REGISTER 9-37: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 U-0 U-0 R/W-0 — — RP31R5 bit 15 U-0 U-0 R/W-0 — — RP30R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 149
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 150
... PIC24FJ256GB110 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 151
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...
Page 152
... PIC24FJ256GB110 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset (1) Read TMR2 (TMR4) (1) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...
Page 153
... Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer3. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1x Gate Sync 01 00 ...
Page 154
... PIC24FJ256GB110 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...
Page 155
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 (1) — — ...
Page 156
... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 154 Preliminary © 2008 Microchip Technology Inc. ...
Page 157
... Section 34. “Input Capture Dedicated Timer” (DS39722). Devices in the PIC24FJ256GB110 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and oper- ating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: • ...
Page 158
... PIC24FJ256GB110 FAMILY 12.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The ...
Page 159
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 R-0, HC ...
Page 160
... PIC24FJ256GB110 FAMILY REGISTER 12-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 HS U-0 ICTRIG TRIGSTAT — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 ...
Page 161
... PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”. Devices in the PIC24FJ256GB110 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and oper- ating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications ...
Page 162
... PIC24FJ256GB110 FAMILY FIGURE 13-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Sources Sync Logic Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” ...
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... TON bit for the selected timer which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set the OC32 (OCyCON2< ...
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... PIC24FJ256GB110 FAMILY 13.3 Pulse-Width Modulation (PWM) Mode In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare module for PWM operation: 1 ...
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... T ; Doze mode and PLL are disabled. CY OSC © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i ...
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... PIC24FJ256GB110 FAMILY TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (F PWM Frequency 7.6 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2, Doze mode and PLL are disabled. CY OSC TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30 ...
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... The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. 2: OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are double-buffered only in PWM modes. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OCTSEL2 OCTSEL1 ...
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... PIC24FJ256GB110 FAMILY REGISTER 13-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN bit 15 R/W-0 R/W-0 HS R/W-0 OCTRIG TRIGSTAT OCTRIS bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FLTMD: Fault Mode Select bit ...
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... Not synchronized to any other module Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) (2) (2) (2) (2) (2) ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 168 Preliminary © 2008 Microchip Technology Inc. ...
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... EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola’s SPI and SIOP interfaces. All devices of the PIC24FJ256GB110 family include three SPI modules The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer ...
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... PIC24FJ256GB110 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. ...
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... SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
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... PIC24FJ256GB110 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0 R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
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... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 173 ...
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... PIC24FJ256GB110 FAMILY REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — ...
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... PIC24FJ256GB110 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
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... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...
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... PIC24FJ256GB110 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 14-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2, Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies shown in kHz. DS39897B-page 178 ...
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... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
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... PIC24FJ256GB110 FAMILY 2 FIGURE 15-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39897B-page 180 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
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... Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.3 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
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... PIC24FJ256GB110 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module ...
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... SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C master. Applicable during master receive master. Applicable during master ...
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... PIC24FJ256GB110 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ACKSTAT: Acknowledge Status bit ...
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... TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C slave device address byte. Preliminary DS39897B-page 185 ...
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... PIC24FJ256GB110 FAMILY REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
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... The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
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... PIC24FJ256GB110 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: ...
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... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 16.2 “Transmitting in 8-Bit Data Mode”). ...
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... PIC24FJ256GB110 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN1:UEN0 0 = UARTx is disabled ...
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... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 191 ...
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... PIC24FJ256GB110 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved ...
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... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 193 ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 194 Preliminary © 2008 Microchip Technology Inc. ...
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... Family Reference ”Section 27. USB On-The-Go (OTG)”. PIC24FJ256GB110 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral device USB embedded host with limited host capabilities ...
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... PIC24FJ256GB110 FAMILY FIGURE 17-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up Host Pull-down (1) D+ (1) D- (1) USBID (1) VMIO (1) VPIO (1) DMH (1) DPH (1) DMLN (1) DPLN (1) RCV (1) USBOEN (1) V BUSON SRP Charge V BUS SRP Discharge V USB Transceiver Power 3.3V ( CMPST ( CMPST (1) V BUSST CPCON (1) V Note 1: Pins are multiplexed with digital I/O and other device features ...
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... Descriptor Note: Memory area not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Depending on the endpoint buffering configuration used, there are sets of buffer descriptors, for a total of 256 bytes minimum, the BDT must be at least 8 bytes long. This is because the USB specifica- tion mandates that every device must have Endpoint 0 with both input and output for initial setup ...
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... PIC24FJ256GB110 FAMILY 17.1.1 BUFFER OWNERSHIP Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory ...