PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 177

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 14-2:
REGISTER 14-3:
© 2008 Microchip Technology Inc.
bit 4-2
bit 1-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
2:
3:
4:
If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin
Select” for more information.
If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin
Select” for more information.
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select”
for more information.
SPRE2:SPRE0: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
...
000 = Secondary prescale 8:1
PPRE1:PPRE0: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer enabled
0 = Enhanced Buffer disabled (Legacy mode)
SPIFSD
R/W-0
U-0
—
SPI
SPIxCON2: SPIx CONTROL REGISTER 2
X
CON1: SPIx CONTROL REGISTER 1 (CONTINUED)
W = Writable bit
‘1’ = Bit is set
SPIFPOL
R/W-0
U-0
—
PIC24FJ256GB110 FAMILY
U-0
U-0
—
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
SPIFE
R/W-0
U-0
—
DS39897B-page 175
SPIBEN
R/W-0
U-0
—
bit 8
bit 0