PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet

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... PIC24FJ256GB110 Family  2009 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) DS39897C ...

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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... PIC24FJ256GB110 100 256K 16K  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY High-Performance CPU: • Modified Harvard Architecture • MIPS Operation at 32 MHz • 8 MHz Internal Oscillator • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16-Bit Working Register Array • ...

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... PIC24FJ256GB110 FAMILY Peripheral Features: • Peripheral Pin Select (PPS): - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer 2 • ...

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... REF Legend: Shaded pins indicate pins tolerant +5.5 VDC. RPn represents remappable pins for the Peripheral Pin Select feature. Note 1: For QFN devices, the backplane on the underside of the device must also be connected to V  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ64GB106 ...

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... PIC24FJ256GB110 FAMILY Pin Diagram (80-Pin TQFP) 1 PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 2 SDA3/PMD7/CN65/RE7 3 RPI38/CN45/RC1 4 RPI40/CN47/RC3 5 PMA5/RP21/C1IND/CN8/RG6 6 C1INC/RP26/PMA4/CN9/RG7 7 C2IND/RP19/PMA3/CN10/RG8 8 MCLR 9 C2INC/RP27/PMA2/CN11/RG9 TMS/RPI33/CN66/RE8 13 TDO/RPI34/CN67/RE9 14 PGEC3/AN5/C1INA/V /RP18/CN7/RB5 BUSON 15 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 16 AN3/C2INA/VPIO/CN5/RB3 17 AN2/C2INB/VMIO/RP13/CN4/RB2 18 PGEC1/AN1/RP1/CN3/RB1 19 PGED1/AN0/RP0/CN2/RB0 20 Legend: Shaded pins indicate pins tolerant +5.5 VDC. RPn represents remappable pins for the Peripheral Pin Select feature. ...

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... PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 AN3/C2INA/VPIO/CN5/RB3 22 AN2/C2INB/VMIO/RP13/CN4/RB2 23 PGEC1/AN1/RP1/CN3/RB1 24 PGED1/AN0/RP0/CN2/RB0 25 Legend: Shaded pins indicate pins tolerant +5.5 VDC. RPn and RPIn represent remappable pins for the Peripheral Pin Select features.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 SOSCO/T1CK/C3INC/RPI37/ 74 CN0/RC14 73 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 72 RP12/PMCS1/CN56/RD11 ...

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... PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 27 3.0 CPU ........................................................................................................................................................................................... 33 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory .............................................................................................................................................................. 63 6.0 Resets ........................................................................................................................................................................................ 71 7.0 Interrupt Controller ..................................................................................................................................................................... 77 8.0 Oscillator Configuration ............................................................................................................................................................ 121 9.0 Power-Saving Features ............................................................................................................................................................ 131 10.0 I/O Ports ................................................................................................................................................................................... 133 11 ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY DS39897C-page 9 ...

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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 10  2009 Microchip Technology Inc. ...

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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...

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... Details on Individual Family Members Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in four ways: 1 ...

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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

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... PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

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... TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

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... PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control OSCO/CLKO OSCI/CLKI Power-up Timing Timer Generation Oscillator Start-up Timer FRC/LPRC ...

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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin 80-Pin TQFP, QFN TQFP AN0 16 20 AN1 15 19 AN2 14 18 AN3 13 17 AN4 12 16 AN5 11 15 AN6 17 21 AN7 18 22 AN8 21 27 AN9 22 28 AN10 23 29 AN11 24 30 AN12 27 33 AN13 ...

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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP, QFN TQFP CN0 48 60 CN1 47 59 CN2 16 20 CN3 15 19 CN4 14 18 CN5 13 17 CN6 12 16 CN7 11 15 CN8 4 6 CN9 5 7 CN10 6 8 CN11 ...

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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP, QFN TQFP CN43 — 52 CN44 — 53 CN45 — 4 CN46 — — CN47 — 5 CN48 — — CN49 46 58 CN50 49 61 CN51 50 62 CN52 51 63 CN53 42 54 CN54 43 55 ...

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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP, QFN TQFP DMH 46 58 DMLN 42 54 DPH 50 62 DPLN 43 55 ENVREG 57 71 INT0 46 58 MCLR 7 9 OSCI 39 49 OSCO 40 50 PGEC1 15 19 PGED1 16 20 PGEC2 ...

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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP, QFN TQFP PMD0 60 76 PMD1 61 77 PMD2 62 78 PMD3 63 79 PMD4 64 80 PMD5 1 1 PMD6 2 2 PMD7 3 3 PMRD 53 67 PMWR 52 66 RA0 — — RA1 — — ...

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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP, QFN TQFP RC1 — 4 RC2 — — RC3 — 5 RC4 — — RC12 39 49 RC13 47 59 RC14 48 60 RC15 40 50 RCV 18 22 RD0 46 58 RD1 ...

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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP, QFN TQFP RF0 58 72 RF1 59 73 RF2 — 42 RF3 33 41 RF4 31 39 RF5 32 40 RF8 — 43 RF12 — — RF13 — — RG0 — 75 RG1 — 74 RG2 37 47 ...

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... PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin TQFP, QFN TQFP RP20 53 67 RP21 4 6 RP22 51 63 RP23 50 62 RP24 49 61 RP25 52 66 RP26 5 7 RP27 8 10 RP28 12 16 RP29 30 36 RP30 — 42 RP31 — ...

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... TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin TQFP, QFN TQFP BUS BUSON BUSST CAP CMPST CMPST CPCON V 10, 26, 38 12, 32 16, 37 DDCORE VMIO 14 18 VPIO REF REF V 9, 25, 41 11, 31, 51 15, 36, 45 USB Legend: TTL = TTL input buffer ANA = Analog level input/output  ...

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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 26  2009 Microchip Technology Inc. ...

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... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24FJ256GB110 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...

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... PIC24FJ256GB110 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...

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... When the regulator is disabled, the V CAP must be tied to a voltage supply at the V Refer to Section 29.0 “Electrical Characteristics” for information on V and DDCORE  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 2- 0.1 0.01 0.001 0.01 Note: Data for Murata GRM21BF50J106ZE01 shown. ...

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... PIC24FJ256GB110 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...

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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...

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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 32  2009 Microchip Technology Inc. ...

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... Instructions are associated with predefined addressing modes depending upon their functional requirements.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...

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... PIC24FJ256GB110 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...

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... W12 W13 W14 W15 22 Registers or bits shaded for PUSH.S and POP.S instructions.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...

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... PIC24FJ256GB110 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...

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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...

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... PIC24FJ256GB110 FAMILY 3.3.2 DIVIDER The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...

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... Program Address Space The program address memory PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES PIC24FJ64GB1XX PIC24FJ128GB1XX GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table ...

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... On device Reset, the config- uration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration PIC24FJ256GB110 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1. The Configuration Words in program memory are a compact format ...

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... Section 4.3.3 “Reading Data from Program Memory Using Program Space Visibility”). FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES MSB Address 0001h 07FFh ...

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... PIC24FJ256GB110 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the ...

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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0054 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0056 CN31PDE CN30PDE CN29PDE CN28PDE (1) (2) (1) (1) CNPD3 0058 CN47PDE CN46PDE CN45PDE CN44PDE CNPD4 005A ...

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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...

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TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ...

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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — ...

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TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 ...

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TABLE 4-10: UART REGISTER MAPS File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...

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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — ODCA 02C6 ODA15 ODA14 — ...

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TABLE 4-16: PORTE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISE 02E0 — — — — PORTE 02E2 — — — — LATE 02E4 — — — — ODCE 02E6 — — — — ...

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TABLE 4-20: ADC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...

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TABLE 4-22: USB OTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1OTGIR 0480 — — — — U1OTGIE 0482 — — — — U1OTGSTAT 0484 — — — — U1OTGCON 0486 — ...

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TABLE 4-22: USB OTG REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1EP0 04AA — — — — U1EP1 04AC — — — — U1EP2 04AE — — — — U1EP3 04B0 ...

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TABLE 4-24: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC Legend: — = unimplemented, ...

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TABLE 4-27: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — INT1R5 INT1R4 RPINR1 0682 — — INT3R5 INT3R4 RPINR2 0684 — — — — RPINR3 0686 — — ...

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TABLE 4-28: SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...

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... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++]  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...

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... PIC24FJ256GB110 FAMILY TABLE 4-31: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG< ...

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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...

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... PIC24FJ256GB110 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i ...

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... Run-Time Self-Programming (RTSP) • JTAG • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ256GB110 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx ...

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... PIC24FJ256GB110 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...

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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) U-0 U-0 — — (1) U-0 ...

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... PIC24FJ256GB110 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...

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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0]  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...

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... PIC24FJ256GB110 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS (C LANGUAGE CODE example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 unsigned int offset; unsigned int i; unsigned long progAddr = 0xXXXXXX; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON = 0x4001; //Set up pointer to the first memory location to be written TBLPAG = progAddr> ...

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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘0011’. The write is performed by executing the unlock sequence and setting the WR bit, as shown in Example 5-7 ...

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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 70  2009 Microchip Technology Inc. ...

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... Illegal Opcode Configuration Mismatch Uninitialized W Register  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...

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... PIC24FJ256GB110 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0, HS R/W-0, HS U-0 TRAPR IOPUWR — bit 15 R/W-0, HS R/W-0, HS R/W-0 EXTR SWR SWDTEN bit 7 Legend Hardware settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit ...

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... MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...

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... PIC24FJ256GB110 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source (6) POR EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL All Others Any Clock Note Power-on Reset delay. ...

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... FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associ- ated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset ...

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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 76  2009 Microchip Technology Inc. ...

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... These are summarized in Table 7-1 and Table 7-2.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...

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... PIC24FJ256GB110 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...

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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah ...

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... UART4 Receiver UART4 Transmitter USB Interrupt 7.3 Interrupt Control and Status Registers The PIC24FJ256GB110 family of devices implements a total of 37 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS5 • IEC0 through IEC5 • IPC0 through IPC23 (except IPC14 and IPC17) • ...

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... See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 — — ...

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... PIC24FJ256GB110 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...

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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...

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... PIC24FJ256GB110 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 85

... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...

Page 86

... PIC24FJ256GB110 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 87

... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 88

... PIC24FJ256GB110 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 89

... Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF R/W-0 ...

Page 90

... PIC24FJ256GB110 FAMILY REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 91

... Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 (1) T5IE T4IE ...

Page 92

... PIC24FJ256GB110 FAMILY REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “ ...

Page 93

... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE U-0 ...

Page 94

... PIC24FJ256GB110 FAMILY REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 R/W-0 R/W-0 (1) — INT4IE INT3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...

Page 95

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...

Page 96

... PIC24FJ256GB110 FAMILY REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 — — IC9IE bit 15 R/W-0 R/W-0 R/W-0 U4ERIE USB1IE MI2C3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 97

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — ...

Page 98

... PIC24FJ256GB110 FAMILY REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP2 T2IP1 bit 15 U-0 R/W-1 R/W-0 — IC2IP2 IC2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP< ...

Page 99

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — ...

Page 100

... PIC24FJ256GB110 FAMILY REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP2 AD1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...

Page 101

... SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — ...

Page 102

... PIC24FJ256GB110 FAMILY REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP2 IC8IP1 bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...

Page 103

... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — ...

Page 104

... PIC24FJ256GB110 FAMILY REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 — INT2IP2 INT2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP< ...

Page 105

... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — ...

Page 106

... PIC24FJ256GB110 FAMILY REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 — IC5IP2 IC5IP1 bit 15 U-0 R/W-1 R/W-0 — IC3IP2 IC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP< ...

Page 107

... IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 U-0 R/W-1 OC5IP0 — ...

Page 108

... PIC24FJ256GB110 FAMILY REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PMPIP2 PMPIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP< ...

Page 109

... SI2C2P<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 U-0 U-0 SI2C2P0 — ...

Page 110

... PIC24FJ256GB110 FAMILY REGISTER 7-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT3IP2 INT3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP< ...

Page 111

... RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — ...

Page 112

... PIC24FJ256GB110 FAMILY REGISTER 7-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 — U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP< ...

Page 113

... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...

Page 114

... PIC24FJ256GB110 FAMILY REGISTER 7-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 — U3TXIP2 U3TXIP1 bit 15 U-0 R/W-1 R/W-0 — U3ERIP2 U3ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP< ...

Page 115

... SI2C3P<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 U-0 R/W-1 MI2C3P0 — ...

Page 116

... PIC24FJ256GB110 FAMILY REGISTER 7-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 — SPI3IP2 SPI3IP1 bit 15 U-0 R/W-1 R/W-0 — U4TXIP2 U4TXIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 SPI3IP< ...

Page 117

... OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 IC9IP0 — ...

Page 118

... PIC24FJ256GB110 FAMILY REGISTER 7-39: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 CPUIRQ — VHOLD bit 15 U-0 R-0 R-0 — VECNUM6 VECNUM5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit interrupt request has occurred but has not yet been Acknowledged by the CPU ...

Page 119

... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...

Page 120

... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 120  2009 Microchip Technology Inc. ...

Page 121

... For more information, refer to the “PIC24F Family Reference Section 6. “Oscillator” (DS39700). The oscillator system for PIC24FJ256GB110 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 8-1: PIC24FJ256GB110 FAMILY CLOCK DIAGRAM ...

Page 122

... PIC24FJ256GB110 FAMILY 8.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator ...

Page 123

... Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The OSCCON register (Register 8-1) is the main con- trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. ...

Page 124

... PIC24FJ256GB110 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...

Page 125

... Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...

Page 126

... PIC24FJ256GB110 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...

Page 127

... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. ...

Page 128

... USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ256GB110 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals ...

Page 129

... In addition to the CLKO output (F module in certain oscillator modes, the device clock in the PIC24FJ256GB110 family devices can also be config- ured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configura- tions and allows the user to select a greater range of clock submultiples to drive external devices in the application ...

Page 130

... PIC24FJ256GB110 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 ROEN — ROSSLP bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROEN: Reference Oscillator Output Enable bit ...

Page 131

... Family Reference Section 10. “Power-Saving Features” (DS39698). The PIC24FJ256GB110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • ...

Page 132

... PIC24FJ256GB110 FAMILY 9.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “ ...

Page 133

... Data Latch Read LAT Read PORT  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 134

... PIC24FJ256GB110 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits con- figures the corresponding pin to act as an open-drain output ...

Page 135

... Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB110 family of devices to generate interrupt requests to the processor in response to a Change-Of-State (COS) on selected input pins. This feature is capable of detecting input Change-Of-States even in Sleep mode, when the clocks are disabled. Depending on the device pin ...

Page 136

... PIC24FJ256GB110 FAMILY 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These include general serial communications (UART and SPI), general pur- pose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs ...

Page 137

... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Register INT1 RPINR0 INT2 RPINR1 INT3 RPINR1 INT4 ...

Page 138

... PIC24FJ256GB110 FAMILY TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) (1) Output Function Number 37-63 Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. ...

Page 139

... PIC24FJ256GB110 Family Devices Although the PPS registers theoretically allow for remappable I/O pins, not all of these are imple- mented in all devices. For PIC24FJ256GB110 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices ...

Page 140

... PIC24FJ256GB110 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’ ...

Page 141

... PERIPHERAL PIN SELECT REGISTERS The PIC24FJ256GB110 family of devices implements a total of 37 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (21) • Output Remappable Peripheral Registers (16) REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 — — INT1R5 ...

Page 142

... PIC24FJ256GB110 FAMILY REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-1 — — INT4R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...

Page 143

... IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 T5CKR3 T5CKR2 ...

Page 144

... PIC24FJ256GB110 FAMILY REGISTER 10-7: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 — — IC4R5 bit 15 U-0 U-0 R/W-1 — — IC3R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 145

... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC8R4 IC8R3 ...

Page 146

... PIC24FJ256GB110 FAMILY REGISTER 10-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 — — IC9R5 bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 147

... U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 U1CTSR3 ...

Page 148

... PIC24FJ256GB110 FAMILY REGISTER 10-15: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 — — SCK1R5 bit 15 U-0 U-0 R/W-1 — — SDI1R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 149

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 R/W-1 ...

Page 150

... PIC24FJ256GB110 FAMILY REGISTER 10-19: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 — — U4CTSR5 bit 15 U-0 U-0 R/W-1 — — U4RXR5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 151

... Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — ...

Page 152

... PIC24FJ256GB110 FAMILY REGISTER 10-23: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 — — RP3R5 bit 15 U-0 U-0 R/W-0 — — RP2R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 153

... Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP8 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP7R4 RP7R3 RP7R2 ...

Page 154

... PIC24FJ256GB110 FAMILY REGISTER 10-27: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 — — RP11R5 bit 15 U-0 U-0 R/W-0 — — RP10R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 155

... Peripheral output number n is assigned to pin, RP17 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP16 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) (1) ...

Page 156

... PIC24FJ256GB110 FAMILY REGISTER 10-31: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 — — RP19R5 bit 15 U-0 U-0 R/W-0 — — RP18R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 157

... Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP23R4 RP23R3 RP23R2 ...

Page 158

... PIC24FJ256GB110 FAMILY REGISTER 10-35: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 — — RP27R5 bit 15 U-0 U-0 R/W-0 — — RP26R5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...

Page 159

... RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Table 10-3 for peripheral function numbers) Note 1: Unimplemented on 64-pin and 80-pin devices; read as ‘0’. 2: Unimplemented on 64-pin devices; read as ‘0’.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) (1) ...

Page 160

... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 160  2009 Microchip Technology Inc. ...

Page 161

... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 162

... PIC24FJ256GB110 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...

Page 163

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...

Page 164

... PIC24FJ256GB110 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset (1) Read TMR2 (TMR4) (1) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...

Page 165

... Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer3.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1x Gate Sync 01 00 ...

Page 166

... PIC24FJ256GB110 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...

Page 167

... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 (1) — — ...

Page 168

... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 168  2009 Microchip Technology Inc. ...

Page 169

... Section 34. “Input Capture Dedicated Timer” (DS39722). Devices in the PIC24FJ256GB110 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: • ...

Page 170

... PIC24FJ256GB110 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The ...

Page 171

... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select”.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 ICTSEL0 ...

Page 172

... PIC24FJ256GB110 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 HS U-0 ICTRIG TRIGSTAT — bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...

Page 173

... For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Compare with Dedicated Timers” (DS39723). Devices in the PIC24FJ256GB110 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and oper- ating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications ...

Page 174

... PIC24FJ256GB110 FAMILY 14.2 Compare Operations In Compare mode (Figure 14-1), the output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. Configure the OCx output for one of the available Peripheral Pin Select pins ...

Page 175

... Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode registers In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation ...

Page 176

... PIC24FJ256GB110 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Logic Sync Sources Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” ...

Page 177

... Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2, Doze mode and PLL are disabled. CY OSC  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY ( F CY log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. ...

Page 178

... PIC24FJ256GB110 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 — — OCSIDL bit 15 R/W-0 U-0 U-0 ENFLT0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...

Page 179

... Output compare peripheral x connected to OCx pin Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 U-0 OCINV — — ...

Page 180

... PIC24FJ256GB110 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module 11110 = Input Capture 9 11101 = Input Capture 6 (2) 11100 = CTMU (2) 11011 = A/D 11010 = Comparator 3 11001 = Comparator 2 11000 = Comparator 1 10111 = Input Capture 4 10110 = Input Capture 3 ...

Page 181

... EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola’s SPI and SIOP interfaces. All devices of the PIC24FJ256GB110 family include three SPI modules The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer ...

Page 182

... PIC24FJ256GB110 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. ...

Page 183

... SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...

Page 184

... PIC24FJ256GB110 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0 HS R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...

Page 185

... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY DS39897C-page 185 ...

Page 186

... PIC24FJ256GB110 FAMILY REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...

Page 187

... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — ...

Page 188

... PIC24FJ256GB110 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (2) (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...

Page 189

... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave)  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...

Page 190

... PIC24FJ256GB110 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 15-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2, Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies shown in kHz. DS39897C-page 190 ...

Page 191

... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 16-1.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...

Page 192

... PIC24FJ256GB110 FAMILY 2 FIGURE 16-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39897C-page 192 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...

Page 193

... Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.3 Slave Address Masking The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...

Page 194

... PIC24FJ256GB110 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module ...

Page 195

... SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C master. Applicable during master receive master. Applicable during master ...

Page 196

... PIC24FJ256GB110 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ...

Page 197

... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C slave device address byte. DS39897C-page 197 ...

Page 198

... PIC24FJ256GB110 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...

Page 199

... The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...

Page 200

... PIC24FJ256GB110 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: ...