PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 238

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GB110 FAMILY
18.7.3
REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15)
DS39897C-page 238
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
LSPD
R/W-0
U-0
—
(1)
These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits
are always unimplemented and read as ‘0’.
USB ENDPOINT MANAGEMENT
REGISTERS
Unimplemented: Read as ‘0’
LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)
1 = Direct connection to a low-speed device enabled
0 = Direct connection to a low-speed device disabled
RETRYDIS: Retry Disable bit (U1EP0 only)
1 = Retry NAK transactions disabled
0 = Retry NAK transactions enabled; retry done in hardware
Unimplemented: Read as ‘0’
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers allowed
0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also allowed.
For all other combinations of EPTXEN and EPRXEN:
This bit is ignored.
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive enabled
0 = Endpoint n receive disabled
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit enabled
0 = Endpoint n transmit disabled
EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
RETRYDIS
R/W-0
U-0
—
(1)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
EPCONDIS
R/W-0
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPRXEN
R/W-0
U-0
—
EPTXEN
(1)
R/W-0
U-0
—
 2009 Microchip Technology Inc.
x = Bit is unknown
EPSTALL
R/W-0
U-0
—
EPHSHK
R/W-0
U-0
—
bit 8
bit 0