PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet

IC PIC MCU FLASH 256K 100TQFP

PIC24FJ256GB110-I/PF

Manufacturer Part Number
PIC24FJ256GB110-I/PF
Description
IC PIC MCU FLASH 256K 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
83
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
84
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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1.0
This document defines the programming specification
for the PIC24FJXXXGA1/GB1 families of 16-bit
microcontroller devices. This programming specification
is required only for those developing programming
support
Customers using only one of these devices should use
development tools that already provide support for
device programming.
This specification includes programming specifications
for the following devices:
2.0
There
PIC24FJXXXGA1/GB1 families of devices discussed
in this programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
© 2007 Microchip Technology Inc.
• PIC24FJ256GA106
• PIC24FJ256GA108
• PIC24FJ256GA110
• PIC24FJ192GA106
• PIC24FJ192GA108
• PIC24FJ192GA110
• PIC24FJ128GA106
• PIC24FJ128GA108
• PIC24FJ128GA110
• PIC24FJ64GB106
• PIC24FJ64GB110
(Enhanced ICSP)
PIC24FJXXXGA1/GB1 Families Flash Programming
are
DEVICE OVERVIEW
PROGRAMMING OVERVIEW
OF THE PIC24FJXXXGA1/GB1
FAMILIES
for
two
the
methods
PIC24FJXXXGA1/GB1
• PIC24FJ256GB106
• PIC24FJ256GB108
• PIC24FJ256GB110
• PIC24FJ192GB106
• PIC24FJ192GB108
• PIC24FJ192GB110
• PIC24FJ128GB106
• PIC24FJ128GB108
• PIC24FJ128GB110
• PIC24FJ64GB108
of
PIC24FJXXXGA1/GB1
programming
families.
Specification
the
The
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, pro-
gram and verify the chip through a small command set.
The command set allows the programmer to program
the PIC24FJXXXGA1/GB1 devices without having to
deal with the low-level programming protocols of the
chip.
FIGURE 2-1:
This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming – Enhanced
ICSP” describes the Run-Time Self-Programming
(RTSP) method. Section 3.0 “Device Programming –
ICSP” describes the In-Circuit Serial Programming
method.
Programmer
Enhanced
In-Circuit
PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
PIC24FJXXXGA1/GB1
Serial
On-Chip Memory
Programming
Executive
DS39907A-page 1
Programming

PIC24FJ256GB110-I/PF Summary of contents

Page 1

... This specification includes programming specifications for the following devices: • PIC24FJ256GA106 • PIC24FJ256GB106 • PIC24FJ256GA108 • PIC24FJ256GB108 • PIC24FJ256GA110 • PIC24FJ256GB110 • PIC24FJ192GA106 • PIC24FJ192GB106 • PIC24FJ192GA108 • PIC24FJ192GB108 • PIC24FJ192GA110 • PIC24FJ192GB110 • PIC24FJ128GA106 • PIC24FJ128GB106 • ...

Page 2

... V SS Regulator Disabled (V tied DDCORE (1) 2.5V PIC24FJXXXGA1/GB1 V DD ENVREG V /V DDCORE CAP V SS Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of V and DDCORE © 2007 Microchip Technology Inc ...

Page 3

... RG8 MCLR RG9 V PGEC3/AN5/RP18/C1INA/CN7/RB5 PGED3/AN4/RP28/C1INB/CN6/RB4 RB3 RB2 PGEC1/AN1/RP1/V -/CN3/RB1 REF PGED1/AN0/RP0/PMA6/V +/ CN2/RB0 REF © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 During Programming Pin Type P Programming Enable I Enable for On-Chip Voltage Regulator P Power Supply P Ground P Regulated Power Supply for Core I Programming Pin Pairs 1, 2 and 3: Serial Clock ...

Page 4

... RG6 RG7 RG8 MCLR RG9 V V CN66/RE8 CN67/RE9 PGEC3/AN5/RP18/ C1INA/CN7/RB5 PGED3/AN4/RP28/ C1INB/CN6/RB4 RB3 RB2 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0 DS39907A-page PIC24FJXXXGA108 RC14 59 RC13 58 RD0 57 RD11 56 RD10 55 RD9 54 RD8 53 RA15 52 RA14 RC15 50 RC12 RG2 47 RG3 46 RF6 45 RF7 44 RF8 43 RF2 42 RF3 41 © 2007 Microchip Technology Inc. ...

Page 5

... FIGURE 2-5: PIN DIAGRAMS (CONTINUED) 100-Pin TQFP RG15 V RE5 RE6 RE7 RC1 RC2 RC3 RC4 RG6 RG7 RG8 MCLR RG9 V V RA0 RE8 RE9 PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 RB3 RB2 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0 © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 PIC24FJXXXGA110 RC14 74 RC13 73 RD0 72 RD11 ...

Page 6

... REF PGED1/AN0/RP0/PMA6/V +/ REF DS39907A-page 6 1 RE5 RE6 2 RE7 3 RG6 4 RG7 5 RG8 6 MCLR 7 PIC24FJXXXGB106 RG9 RB3 13 RB2 14 -/CN3/RB1 15 CN2/RB0 16 48 RC14 47 RC13 46 RD0 45 RD11 44 RD10 43 RD9 42 RD8 RC15 39 RC12 D+/RG2 36 D-/RG3 35 V USB 34 V BUS 33 RF3 © 2007 Microchip Technology Inc. ...

Page 7

... FIGURE 2-7: PIN DIAGRAMS (CONTINUED) 80-Pin TQFP MCLR CN66/RE8 CN67/RE9 PGEC3/AN5/RP18/VBUSON/ C1INA/CN7/RB5 PGED3/AN4/RP28/USBOEN/ C1INB/CN6/RB4 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0 © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 1 RE5 RE6 2 RE7 3 4 RC1 5 RC3 6 RG6 7 RG7 8 RG8 9 10 RG9 PIC24FJXXXGB108 RB3 17 RB2 RC14 59 RC13 58 RD0 57 RD11 56 RD10 ...

Page 8

... RA0 RE8 RE9 PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 RB3 RB2 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0 DS39907A-page PIC24FJXXXGB110 RC14 74 RC13 73 RD0 72 RD11 71 RD10 70 RD9 69 RD8 68 RA15 67 RA14 RC15 64 RC12 RA5 61 RA4 60 RA3 59 RA2 58 D+/RG2 57 D-/RG3 USB 54 V BUS RF8 53 RF2 52 RF3 51 © 2007 Microchip Technology Inc. ...

Page 9

... PIC24FJ192GB1XX PIC24FJ256GA1XX 02ABFEh (87K) PIC24FJ256GB1XX © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 The last three implemented program memory locations are reserved for the Flash Configuration Words. In PIC24FJXXXGB1 family devices, the last three loca- tions are used for the Configuration Words; for PIC24FJXXXGA1 devices, the last two locations are used ...

Page 10

... User Flash (1) Code Memory (1) 0XXXF9h (1) 0XXXFAh Flash Configuration Words (1) 0XXXFEh (1) 0XXX00h Reserved 7FFFFEh 800000h Executive Code Memory (1024 x 24-bit) 8007FAh Diagnostic and Calibration 8007F0h Words (8 x 24-bit) 800800h Reserved FEFFFEh FF0000h Device 16-bit) FF0002h FF0004h Reserved FFFFFEh © 2007 Microchip Technology Inc. ...

Page 11

... Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. Then, program the code-protect Configuration bits, if required. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ ...

Page 12

... ICSP operation. To prevent this, instructions should be periodically executed to reset the safe space. The opti- mal method to accomplish this is to perform a GOTO 0x200 P4A MSB Execute 24-Bit Instruction, Fetch Next Control Code to a recently modified © 2007 Microchip Technology Inc. ...

Page 13

... Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Note 1: After the contents of VISI are shifted out, the maintain PGDx as an output until the first rising edge of the next clock is received. ...

Page 14

... P7 has elapsed will not be interpreted as valid. . After successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in the high-impedance state ... b29 b28 b27 P1A P1B must be IH P19 P7 © 2007 Microchip Technology Inc. ...

Page 15

... Starting a programming cycle is performed as follows: BSET NVMCON, #WR © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 3.5 Erasing Program Memory The procedure for erasing program memory (all of code memory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 404Fh and executing the programming cycle ...

Page 16

... MOV 0000 883C22 MOV 0000 000000 NOP 0001 <VISI> Clock out contents of the VISI register. 0000 000000 NOP DS39907A-page 16 Description 0x200 #0x404F, W10 W10, NVMCON #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI © 2007 Microchip Technology Inc. ...

Page 17

... MOV 0000 2xxxx5 MOV © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of code memory. Since code memory is programmed 64 instruction words at a time, Steps 4 and 5 are repeated 16 times to load all the write latches (Step 6) ...

Page 18

... NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3-9 until all code memory is programmed. DS39907A-page 18 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 © 2007 Microchip Technology Inc. ...

Page 19

... FIGURE 3-7: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? ...

Page 20

... After verification is finished, the code protection bit can be programmed to a ‘0’ by using a word write to the appropriate Configuration Word. Default Value 7FFFh F7FFh FFFFh © 2007 Microchip Technology Inc. ...

Page 21

... Clock out contents of the VISI register. 0000 000000 NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 5-9 to write CW1. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Description 0x200 <CW2Address15:0>, W7 #0x4003, W10 W10, NVMCON <CW2Address23:16>, W0 W0, TBLPAG #<CW2_VALUE>, W6 W6, [W7++] NVMCON, #WR ...

Page 22

... VISI register, using the REGOUT command. Step 4 is repeated until the desired amount of code memory is read. Description 0x200 #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 #VISI, W7 [W6], [W7] [W6++], [W7++] [++W6], [W7--] [W6++], [W7] 0x200 © 2007 Microchip Technology Inc. ...

Page 23

... GOTO 0000 000000 NOP © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Table 3-10 shows the ICSP programming details for reading the Configuration Words. Note that the TBLPAG register must be loaded with 00h for 64 Kbyte and below devices and 01h for 128 Kbyte and larger ...

Page 24

... P16, should elapse between the last clock and program signals on PGCx and PGDx before removing V FIGURE 3-9: MCLR V DD PGDx Failure, Report PGCx Error EXITING ICSP™ MODE P16 P17 PGD = Input © 2007 Microchip Technology Inc. ...

Page 25

... NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. 0001 <VISI> Clock out contents of the VISI register 0000 000000 NOP © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Description 0x200 #0x80, W0 W0, TBLPAG #0x5BE, W0 #VISI, W1 [W0], [W1] DS39907A-page 25 ...

Page 26

... Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.11 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. © 2007 Microchip Technology Inc. present), the ...

Page 27

... ENTERING ENHANCED ICSP™ MODE P6 P14 MCLR V DD PGDx PGCx P18 © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 4.3 Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. The MCLR pin is briefly driven high, then low. 2. ...

Page 28

... The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. © 2007 Microchip Technology Inc. No Failure Report Error ...

Page 29

... CW1<12> Note 1: Available on PIC24FJXXXGB1XX devices only. 2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 The descriptions for the Configuration bits in the Flash Configuration Words are shown in Table 4-2. Note: Although not implemented with a specific ...

Page 30

... Oscillator input used directly (4 MHz input) Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Watchdog Timer Prescaler bit 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 © 2007 Microchip Technology Inc. ...

Page 31

... WPFP8:WPFP0 CW3<8:0> Note 1: Available on PIC24FJXXXGB1XX devices only. 2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Description Windowed WDT bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode; FWDTEN must be ‘1’ ...

Page 32

... The READP command reads back the programmed Configuration bits and verifies that the programming was successful. code-protect Start ConfigAddress = 0XXXFAh Send PROGP Command Is No PROGP response PASS? Yes Is No ConfigAddress (1) 0XXXFEh? Yes Finish (1) Failure Report Error © 2007 Microchip Technology Inc. ...

Page 33

... Note: Bulk Erasing in ICSP mode is the only way to reprogram code-protect bits from an ON state (‘0’ Off state (‘1’). © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 4.7 Exiting Enhanced ICSP Mode Exiting Program/Verify mode is done by removing V from MCLR, as shown in Figure 4-6 ...

Page 34

... As a safety measure, the programmer should use the command time-outs identified in Table 5-1. If the command time-out expires, the programmer should reset the programming programming the device again. PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE ... LSb executive and start © 2007 Microchip Technology Inc. ...

Page 35

... SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Programming Executive Host Clocks Out Response Processes Command ...

Page 36

... This command is used as a “Sanity Check” to verify that the programming executive is operational. Expected Response (2 words): 1000h 0002h 0 Note: This instruction is not required for programming development purposes only. but is provided for © 2007 Microchip Technology Inc. ...

Page 37

... Expected Response ( – 1)/2 words for N odd): 1100h Device ID Register 1 ... Device ID Register N Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 5.2.7 READP COMMAND Opcode N Reserved Addr_LS ...

Page 38

... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1500h 0002h Note: Refer to Table 2-2 for code memory size information. © 2007 Microchip Technology Inc. 0 Length Addr_MSB Description ...

Page 39

... After the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1600h 0002h © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 5.2.11 QBLANK COMMAND Opcode ...

Page 40

... Since the program- ming executive can only process one command at a time, this field is technically not required. However, it can be used to verify that the programming executive correctly received the command that the programmer transmitted. © 2007 Microchip Technology Inc. 0 QE_Code Description ...

Page 41

... If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other programming executive errors, the QE_Code is 2h. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS ...

Page 42

... This control flow is summarized in Table 5-5. Description 0x200 #0x80, W0 W0, TBLPAG #0x07F0, W1 #0xC, W2 [W1++].[W2++] #0x4042, W0 W0, NVMCON #0x80, W0 W0, TBLPAG #0x0, W1 W1, [W1] NVMCON, #15 0x200 NVMCON, W2 W2, VISI © 2007 Microchip Technology Inc. ...

Page 43

... MOV 0000 2<MSB1:MSB0>1 MOV 0000 2<LSW1>2 MOV 0000 2<LSW2>3 MOV 0000 2<MSB3:MSB2>4 MOV 0000 2<LSW3>5 MOV © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Description #0x80, W0 W0, TBLPAG #0x4003, W1 W1, NVMCON #0x07F0, W1 #0xC, W2 [W2++], [W1++] NVMCON, #15 0x200 NVMCON, W0 W0, VISI #0x4001, W0 W0, NVMCON #0x80, W0 ...

Page 44

... Step 20: Repeat Steps 14-19 until all 16 rows of executive memory have been programmed. On the final row, make sure to initialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to ensure that the calibration is not overwritten. DS39907A-page 44 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #15 0x200 NVMCON, W2 W2, VISI 0x200 © 2007 Microchip Technology Inc. ...

Page 45

... GOTO 0000 000000 NOP Step 6: Repeat Steps 4-5 until all 1024 instruction words of executive memory are read. © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Reading the contents of executive memory can be performed using the same technique described in has been Section 3.8 “Reading Code Memory”. A procedure for reading executive memory is shown in Table 5-6 ...

Page 46

... PIC24FJ192GA108 PIC24FJ256GA108 PIC24FJ128GA110 PIC24FJ192GA110 PIC24FJ256GA110 PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 Bit FAMID<7:0> — MAJRV<2:0> Description Encodes the family ID of the device Encodes the individual ID of the device Encodes the major revision number of the device ...

Page 47

... To Be Determined Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2); CW3 is (last location – 4). © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Table 6-4 describes how to calculate the checksum for each device. All memory locations are summed, one byte at a time, using only their native data size. More ...

Page 48

... PIC24FJ256GB108 Disabled Enabled PIC24FJ64GB110 Disabled Enabled PIC24FJ128GB110 Disabled Enabled PIC24FJ192GB110 Disabled Enabled PIC24FJ256GB110 Disabled Enabled Legend: Item Description SUM[a:b] = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = CFGB = Configuration Block (masked) Byte sum of (CW1 & 0x7BDF + CW2 & 0xF7FF + CW3 & 0xE1FF) ...

Page 49

... Delay Between Programming Executive DLY Command Response Words Note 1: V must be supplied to the V DDCORE Section 2.1 “Power Requirements” for more information. (Minimum V 2.25V must also be supplied to the and V , respectively © 2007 Microchip Technology Inc. PIC24FJXXXGA1/GB1 Min Max V 3.60 DDCORE — 5 — 0 0 — ...

Page 50

... PIC24FJXXXGA1/GB1 NOTES: DS39907A-page 50 © 2007 Microchip Technology Inc. ...

Page 51

... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 52

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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