PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 128

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GB110 FAMILY
9.4.3.3
The control schema of the peripheral pin select is
extremely flexible. Other than systematic blocks that
prevent signal contention caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
9.4.3.4
Although the PPS registers theoretically allow for up to
64 remappable I/O pins, not all of these are imple-
mented in all devices. For PIC24FJ256GB110 family
devices, the maximum number of remappable pins
available are 44, which includes 12 input only pins. In
addition, some pins in the RP and RPI sequences are
unimplemented in lower pin count devices. The
differences
summarized in Table 9-3.
When developing applications that use remappable
pins, users should also keep these things in mind:
• For the RPINRx registers, bit combinations corre-
• For RPORx registers, the bit fields corresponding
9.4.4
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
TABLE 9-3:
DS39897B-page 126
Device Pin Count
sponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it. For all
PIC24FJ256GB110 family devices, this includes
all values greater than 43 (‘101011’).
to an unimplemented pin will also be
unimplemented. Writing to these fields will have
no effect.
100-pin
64-pin
80-pin
CONTROLLING CONFIGURATION
CHANGES
Mapping Limitations
Mapping Exceptions for
PIC24FJ256GB110 Family Devices
in
available
REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GB110 FAMILY DEVICES
Total
28
31
32
remappable
RP Pins (I/O)
RP5, RP15, RP30, RP31
pins
Unimplemented
Preliminary
are
RP31
—
9.4.4.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
9.4.4.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
9.4.4.3
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CW2<4>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the Peripheral Pin Select Control reg-
isters cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the peripheral
pin select registers.
Write 46h to OSCCON<7:0>.
Write 57h to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Total
12
Control Register Lock
Continuous State Monitoring
Configuration Bit Pin Select Lock
1
9
© 2008 Microchip Technology Inc.
RPI Pins
RPI32, RPI39, RPI41
RPI32-36, RPI38-43
Unimplemented
—