PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 284

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
11.25.2
All USB endpoints are implemented as buffers in RAM.
The CPU and USB module have access to the buffers.
To arbitrate access to these buffers between the USB
module and CPU, a semaphore flag system is used.
Each endpoint can be configured for TX and/or RX, and
each has an ODD and an EVEN buffer.
Use of the Buffer Descriptor Table (BDT) allows the
buffers to be located anywhere in RAM, and provides
status flags and control bits. The BDT contains the
address of each endpoint data buffer, as well as infor-
mation about each buffer (see Figure 11-2, Figure 11-3
and Figure 11-4). Each BDT entry is called a Buffer
Descriptor (BD) and is 8 bytes long. All endpoints, rang-
ing from endpoint 0 to the highest endpoint in use, must
have four descriptor entries. Even if all of the buffers for
an endpoint are not used, four descriptors entries are
required for each endpoint.
The USB module calculates a buffer’s location in RAM
using the BDT. The base of the BDT is held in registers
U1BDTP1 through U1BDTP3. The address of the
desired buffer is found by using the endpoint number,
the type (RX/TX) and the ODD/EVEN bit to index into
the BDT. The address held by this entry is the address
of the desired data buffer. Refer to Section 11.24.3.1
“A-Device, the Default Host”.
Each of the 16 endpoints owns two descriptor pairs:
two for packets to transmit, and two for packets
received. Each pair manages two buffers, an EVEN
and an ODD, requiring a maximum of 64 descriptors
(16 * 2 * 2).
Having EVEN and ODD buffers for each direction
allows the CPU to access data in one buffer while the
USB module transfers data to or from the other buffer.
The USB module alternates between buffers, clearing
the UOWN bit in the buffer descriptor automatically
when the transaction for that buffer is complete (see
Section 11.24.3 “OTG Dual Role”). The use of alter-
nating buffers maximizes data throughput by allowing
CPU data access in parallel with data transfer. This
technique is referred to as ping-pong buffering.
Figure 11-2 illustrates how the endpoints are mapped
in the BDT.
11.25.2.1
Each endpoint is controlled by an Endpoint Control reg-
ister, U1EPn, that configures the transfer direction, the
handshake, and the stalling properties of the endpoint.
The Endpoint Control register also allows support of
control transfers.
DS61143B-page 282
Note:
ENDPOINTS AND DESCRIPTORS
The contents of the U1BDTP1-U1BDTP3
registers provide the upper 23 bits of the
32-bit address; therefore, the BTD must
be aligned to a 512-byte boundary (see
Figure 11-2). This address must be the
physical (not virtual) memory address.
Endpoint Control
Advance Information
11.25.2.2
The host performs all transactions through a single
endpoint (Endpoint 0). All other endpoints should be
disabled and other endpoint buffers are not be used.
11.25.2.3
Endpoint 0 must be implemented for a USB device to
be enumerated and controlled. Devices typically imple-
ment additional endpoints to transfer data.
11.25.3
The buffers are shared between the PIC32MX and the
USB module, and are implemented in system memory.
So, a simple semaphore mechanism is used to distin-
guish current ownership of the BD, and associated
buffers, in memory. This semaphore mechanism is
implemented by the UOWN bit in each BD.
The USB module clears the UOWN bit automatically
when the transaction for that buffer is complete. When
the UOWN bit is clear, the descriptor is owned by the
PIC32MX – which may modify the descriptor and buffer
as necessary.
Software must configure the BDT entry for the next
transaction, then set the UOWN bit to return control to
the USB module.
A BD is only valid if the corresponding endpoint has
been enabled in the U1EPn register. The BDT is imple-
mented in data memory, and the BDs are not modified
when the USB module is reset. Initialize the BDs prior
to enabling them through the U1EPn. At a minimum,
the UOWN bits must be cleared prior to being enabled.
In Host mode, BDT initialization is required before the
U1TOK register is written, triggering a transfer.
Note:
In Host mode, Endpoint 0 has additional
bits for auto-retry and hub support.
BUFFER MANAGEMENT
Host Endpoints
Device Endpoints
© 2008 Microchip Technology Inc.