PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.30 Configuring the SOF Threshold
The module counts down the number of bits that could
be transmitted within the current USB full-speed frame.
Since 12,000 bits can be transmitted during the 1 ms
frame time, a counter, not visible to software, is loaded
with the value ‘12,000’ at the start of each frame. The
counter decrements once for each bit time in the frame.
When the counter reaches zero the next frame’s SOF
packet is transmitted, see Figure 11-9.
The SOF threshold register (U1SOF) is used to ensure
that no new tokens are started too close to the end of a
frame. This prevents a conflict with the next frame’s
SOF packet. When the counter reaches the threshold
value of the U1SOF register (the value in the U1SOF
FIGURE 11-9:
Table 11-4 and Table 11-5 show examples of calculat-
ing worst-case bit times.
TABLE 11-4:
© 2008 Microchip Technology Inc.
IN
Turnaround
DATA
Turnaround
HANDSHAKE
Inter-packet
Total
Note 1:
Note 1: While the U1SOF register value is described in terms of bytes, these examples show the result in terms
2:
2: In the second table, the IN, DATA, and HANDSHAKE packets are transmitted at low speed (8 times slower
3: These calculations do not take the possibility that the packet data needs to be bit-stuffed for NRZI encoding
Inter-packet delay of 2. An additional 5.5 bit times of latency is added to represent a worst-case propaga-
tion delay through 5 hubs.
Using 64-bytes maximum packet size for this example calculation.
(1)
of bits.
than full speed).
into account.
Note: Drawing is not to scale.
0 ms
Packet
SOF
EXAMPLE OF SOF THRESHOLD CALCULATION: FULL SPEED
ALLOCATION OF BITS FOR A FULL-SPEED FRAME
SYNC, PID, ADDR, ENDP, CRC5, EOP
SYNC, PID, DATA
SYNC, PID, EOP
Advance Information
1 Full-Speed Frame
(2)
, CRC16, EOP
register is in terms of bytes), no new tokens are started
until after the SOF has been transmitted. Thus, the
USB module attempts to ensure that the USB link is idle
when the SOF token needs to be transmitted.
This implies that the value programmed into the
U1SOF register must reserve enough time to insure the
completion of the worst-case transaction. Typically, the
worst-case transaction is an IN token followed by a
maximum-sized data packet from the target, followed
by the response from the host. If the host is targeting a
low-speed device that is bridging through a full-speed
hub, the transaction will also include the special PRE
token packets.
Fields
PIC32MX FAMILY
SOF Threshold
U1SOF * 8
bit times
1 ms (12,000 bit times)
DS61143B-page 293
SOF
Bits
547
613
35
19
8
2
2