PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 483
PIC32MX360F512L-80I/PT
Manufacturer Part Number
PIC32MX360F512L-80I/PT
Description
IC PIC MCU FLASH 512K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F032H-40IPT.pdf
(626 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F512L-80I/PT
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F512L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX360F512L-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX320F032H-40IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 483 of 626
- Download datasheet (9Mb)
21.5
The RTCC alarm can be configured to generate an
interrupt at every alarm event. Refer to Section 21.3
“Alarm Mode” for details regarding the various alarm
events.
The RTCC module is enabled as a source of interrupts
via the respective RTCC interrupt enable bit:
• RTCCIE (IEC1<15>).
The alarm interrupt is signalled by the corresponding
RTCC interrupt flag bit:
• RTCCIF (IFS1<15>).
This interrupt flag must be cleared in software.
EXAMPLE 21-8:
© 2008 Microchip Technology Inc.
/*
*/
The following code example illustrates an RTCC initialization with interrupts enabled.
When the RTCC alarm interrupt is generated, the cpu will jump to the vector assigned to
RTCC interrupt.
IEC1CLR=0x00008000;
RTCCONCLR=0x8000;
while(RTCCON&0x40);
IFS1CLR=0x00008000;
IPC8CLR=0x1f000000;
IPC8SET=0x0d000000;
IEC1SET=0x00008000;
RTCTIME=0x16153300;
RTCDATE=0x06102705;
RTCALRMCLR=0xCFFF;
ALRMTIME=0x16154300;
ALRMDATE=0x06102705;
RTCALRMSET=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day
RTCCONSET=0x8000;
while(!(RTCCON&0x40));
RTCC Interrupts
RTCC INITIALIZATION WITH INTERRUPTS
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
// disable RTCC interrupts
// turn off the RTCC
// wait for clock to be turned off
// clear RTCC existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable RTCC interrupts
// safe to update time to 16 hr, 15 min, 33 sec
// update the date to Friday 27 Oct 2006
// clear ALRMEN, CHIME, AMASK and ARPT;
// set alarm time to 16 hr, 15 min, 43 sec
// set alarm date to Friday 27 Oct 2006
// turn on the RTCC
// wait for clock to be turned on
Advance Information
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• RTCCIP<2:0> (IPC8<28:26>)
• RTCCIS<1:0> (IPC8<25:24>)
In addition to enabling the RTCC interrupt, an Interrupt
Service Routine, ISR, is required (see Example 21-9)..
Note:
PIC32MX FAMILY
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143B-page 481
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