PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 39

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.2.4
The PIC32MX core includes support for peripheral
interrupts, two software interrupts, and a timer
interrupt.
The PIC32MX MCU uses the MIPS External Interrupt
Controller (EIC) mode, which redefines the way in
which interrupts are handled to provide full support for
an external interrupt controller handling prioritization
and vectoring of interrupts. This presence of this mode
denoted by the VEIC bit in the Config3 register. On the
PIC32MX core, the VEIC bit is always set to ’1’ to
indicate the presence of an external interrupt controller.
The interrupt controller specifies which shadow set
should be used upon entry to a particular vector. The
shadow registers further improve interrupt latency by
avoiding the need to save context when invoking an
interrupt handler.
© 2008 Microchip Technology Inc.
Note:
INTERRUPT HANDLING
Although EIC mode is designated as
“External”, the interrupt controller is
on-chip.
Advance Information
2.2.5
Release 2 of the MIPS32 Architecture optionally
removes the need to save and restore GPRs on entry
to high priority interrupts or exceptions, and to provide
specified processor modes with the same capability.
This is done by introducing multiple copies of the
GPRs, called “shadow sets”, and allowing privileged
software to associate a shadow set with entry to kernel
mode via an interrupt vector or exception. The normal
GPRs are logically considered shadow set zero.
The PIC32MX core implements two sets of registers,
the normal GPRs, and one shadow set. This is
indicated by the SRSCtl
PIC32MX FAMILY
GPR SHADOW REGISTERS
HSS
field.
DS61143B-page 37