PIC18F4585-I/ML Microchip Technology, PIC18F4585-I/ML Datasheet - Page 165

IC MCU FLASH 24KX16 44QFN

PIC18F4585-I/ML

Manufacturer Part Number
PIC18F4585-I/ML
Description
IC MCU FLASH 24KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4585-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
3.25 KB
On-chip Adc
11 bit
Number Of Programmable I/os
44
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Mounting Style
SMD/SMT
Height
0.88 mm
Interface Type
I2C, SPI, EUSART
Length
8 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
8 mm
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
15.0
PIC18F2585/2680 devices have one CCP1 module.
PIC18F4585/4680
(Capture/Compare/PWM) modules. CCP1, discussed in
this chapter, implements standard Capture, Compare
and Pulse-Width Modulation (PWM) modes.
ECCP1 implements an Enhanced PWM mode. The
ECCP1 implementation is discussed in Section 16.0
“Enhanced
Module”.
REGISTER 15-1:
© 2007 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP1) MODULES
bit 7-6
bit 5-4
bit 3-0
Capture/Compare/PWM
devices
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 for CCP1 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC19:DC12) of the duty cycle are found in ECCPR1L.
CCP1M3:CCP1M0: CCP1 Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge or CAN message received (time-stamp)
0101 = Capture mode, every rising edge or CAN message received (time-stamp)
0110 = Capture mode, every 4th rising edge or every 4th CAN message received
0111 = Capture mode, every 16th rising edge or every 16th CAN message received
1000 = Compare mode: initialize CCP1 pin low; on compare match, force CCP1 pin high
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP1 pin low
1010 = Compare mode: generate software interrupt on compare match (CCPIF bit is set,
1011 = Compare mode: trigger special event, reset timer (TMR1 or TMR3, CCP1IF bit is set)
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source.
U-0
(time-stamp)
(time-stamp)
(CCPIF bit is set)
(CCPIF bit is set)
CCP1 pin reflects I/O state)
have
U-0
two
(1)
(1)
PIC18F2585/2680/4585/4680
(ECCP1)
CCP1
DC1B1
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
DC1B0
R/W-0
The CCP1 module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP1 module operation in the
following sections is described with respect to CCP1,
but is equally applicable to ECCP1.
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP1
modules. The operations of PWM mode, described in
Section 15.4 “PWM Mode”, apply to ECCP1 only.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP1M3
R/W-0
CCP1M2 CCP1M1 CCP1M0
R/W-0
x = Bit is unknown
R/W-0
DS39625C-page 163
(1)
(1)
R/W-0
bit 0

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