PIC18F4585-I/ML Microchip Technology, PIC18F4585-I/ML Datasheet - Page 411

• Manufacturer Part Number: PIC18F4585-I/ML
• Description: IC MCU FLASH 24KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 3.25 KB
• On-chip Adc: 11 bit
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 0.88 mm
• Interface Type: I2C, SPI, EUSART
• Length: 8 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDWF
Syntax:
Operands:
Operation:
Status Affected: N, OV, C, DC, Z
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
(W) + ((FSR2) + k) → dest
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0 ≤ k ≤ 95
d ∈ [0,1]
a = 0
The contents of W are added to the contents
of the register indicated by FSR2, offset by the
value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’ (default).
1
1
0010
ADDWF
Read ‘k’
Q2
[k] {,d}
=
=
=
=
=
=
01d0
[OFST] ,0
Process
17h
2Ch
0A00h
20h
37h
20h
Data
Q3
kkkk
destination
Write to
PIC18F2585/2680/4585/4680
Q4
kkkk
Preliminary
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0 ≤ f ≤ 95
0 ≤ b ≤ 7
a = 0
1 → ((FSR2 + k))<b>
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
BSF
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
Read ‘k’
SETF
Read
1000
0110
Q2
Q2
=
=
=
=
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
Process
0Ah
0A00h
55h
D5h
Process
Data
Data
Q3
Q3
DS39625C-page 409
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk