PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet

Page 1

... PIC32MX3XX/4XX Family 64/100-Pin General Purpose and USB © 2009 Microchip Technology Inc. Data Sheet 32-Bit Flash Microcontrollers Preliminary DS61143F ...

Page 2

... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... USB 2.0 Compliant Full Speed Device and On-The-Go (OTG) Controller • USB has a Dedicated DMA Channel • 10 MHz to 40 MHz Crystal Oscillator • Internal 8 MHz and 32 kHz Oscillators © 2009 Microchip Technology Inc. PIC32MX3XX/4XX • Separate PLLs for CPU and USB Clocks 2 • Two I C™ ...

Page 4

... PIC32MX440F512H 64 80 512 + 12 PIC32MX440F128L 100 80 128 + 12 PIC32MX460F256L 100 80 256 + 12 PIC32MX460F512L 100 80 512 + 12 Legend TQFP MR = QFN Note 1: This device features 12 KB Boot Flash memory. 2: See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details. DS61143F-page ENERAL ...

Page 5

... C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/PMA6/AN0/V +/CV +/CN2/RB0 REF REF Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX3XXH ...

Page 6

... C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/PMA6/AN0/V +/CV +/CN2/RB0 REF REF DS61143F-page 4 = Pins are tolerant PIC32MX3XXH Preliminary SOSCO/T1CK/CN0/RC14 48 SOSCI/CN1/RC13 47 46 OC1/RD0 45 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 44 IC2/U1CTS/INT2/RD9 43 IC1/RTCC/INT1/RD8 42 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/BCLK1/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 © 2009 Microchip Technology Inc. ...

Page 7

... T5CK/RC4 PMA5/SCK2/CN8/RG6 10 PMA4/SDI2/CN9/RG7 11 12 PMA3/SDO2/CN10/RG8 MCLR 13 14 PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 18 INT2/RE9 19 20 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 21 22 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 25 PGED1/AN0/CN2/RB0 © 2009 Microchip Technology Inc. PIC32MX3XX/4XX = Pins are tolerant PIC32MX3XXL Preliminary V SS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 ...

Page 8

... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS61143F-page PIC32MX4XXH Preliminary = Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 IC4/PMCS1/PMA14/INT4/RD11 44 IC3/PMCS2/PMA15/INT3/SCL1/RD10 43 IC2/U1CTS//INT2/SDA1/RD9 42 IC1/RTCC/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 D+/RG2 36 D-/RG3 35 VUSB 34 VBUS 33 USBID/RF3 32 © 2009 Microchip Technology Inc. ...

Page 9

... TQFP (USB) PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/EMUD1/PMA6/AN0/V +/CV +/CN2/RB0 REF REF © 2009 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX4XXH Preliminary = Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 ...

Page 10

... C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25 DS61143F-page 8 = Pins are tolerant PIC32MX4XXL Preliminary © 2009 Microchip Technology Inc SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 IC3/SCK1/PMCS2/PMA15/RD10 IC2/SS1/RD9 IC1/RTCC/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3 ...

Page 11

... Comparator Voltage Reference (CVref) ..................................................................................................................................... 97 25.0 Power-Saving Features.............................................................................................................................................................. 99 26.0 Special Features ...................................................................................................................................................................... 101 27.0 Instruction Set .......................................................................................................................................................................... 113 28.0 Development Support............................................................................................................................................................... 121 28.0 Electrical Characteristics .......................................................................................................................................................... 119 29.0 Packaging Information.............................................................................................................................................................. 157 INDEX ................................................................................................................................................................................................ 167 Worldwide Sales and Service ............................................................................................................................................................ 170 © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143F-page 9 ...

Page 12

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS61143F-page 10 Preliminary © 2009 Microchip Technology Inc. ...

Page 13

... Program Flash Memory PORTG Note 1: Some features are not available on all device variants. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX This document contains device-specific information for the PIC32MX3XX/4XX devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC32MX3XX/4XX fam- ilies of devices ...

Page 14

... Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...

Page 15

... PMRD/PMWR O — Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Description Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. ...

Page 16

... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...

Page 17

... REF reference for ADC module is implemented Note: The AV and connected independent of ADC use and ADC voltage reference source. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. See Figure 2-1. SS ...

Page 18

... POR. Preliminary ) and fast signal transitions must IL as shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC32MX JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...

Page 19

... JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Pull-up resistors, series diodes, and capacitors on the TMS, TDO, TDI, and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device ...

Page 20

... Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternately, inputs can be reserved by connecting the pin to V through 10k resistor and configuring SS the pin as an input. Preliminary © 2009 Microchip Technology Inc. ...

Page 21

... MCU BLOCK DIAGRAM MDU Execution Core (RF/ALU/Shift) System Coprocessor © 2009 Microchip Technology Inc. PIC32MX3XX/4XX • MIPS16e™ Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for ...

Page 22

... Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num- ber of cycles until a result is available) for the PIC32MX where data core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. Preliminary © 2009 Microchip Technology Inc. ...

Page 23

... Config Configuration register 16 Config1 Configuration register 1 16 Config2 Configuration register 2 16 Config3 Configuration register 3 © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers ...

Page 24

... EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) AdEL Load address alignment error Load reference to protected address AdES Store address alignment error Store to protected address DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare DS61143F-page 22 Description Preliminary © 2009 Microchip Technology Inc. ...

Page 25

... The majority of the power consumed by the PIC32MX3XX/4XX Family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 3.4 EJTAG Debug Support The PIC32MX3XX/4XX Family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code ...

Page 26

... PIC32MX3XX/4XX NOTES: DS61143F-page 24 Preliminary © 2009 Microchip Technology Inc. ...

Page 27

... Robust bus exception handling to intercept runaway code. • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable and non-cacheable address regions © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 4.1 PIC32MX3XX/4XX Memory Layout PIC32MX3XX/4XX microcontrollers implement two address spaces: Virtual and Physical. All hardware ...

Page 28

... DS61143F-page 26 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM Preliminary 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D008000 0x1D007FFF (2) 0x1D000000 0x00002000 0x00001FFF (2) 0x00000000 © 2009 Microchip Technology Inc. ...

Page 29

... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Physical Memory Map ...

Page 30

... DS61143F-page 28 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM Preliminary 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D020000 0x1D01FFFF (2) 0x1D000000 0x00004000 0x00003FFF (2) 0x00000000 © 2009 Microchip Technology Inc. ...

Page 31

... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Physical Memory Map ...

Page 32

... DS61143F-page 30 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM Preliminary (1) 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D040000 0x1D03FFFF (2) 0x1D000000 0x00008000 0x00007FFF (2) 0x00000000 © 2009 Microchip Technology Inc. ...

Page 33

... FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H, PIC32MX460F512L DEVICES Virtual Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 0xBF800000 Reserved 0xBD080000 0xBD07FFFF Program Flash 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM ...

Page 34

... PERIPHERAL REGISTERS LOCATIONS Table 4-1 through Table 4-25 contain the peripheral address maps for the PIC32MX3XX/4XX device. Pe- ripherals located on the PB Bus are mapped to 512 byte boundaries. Peripherals on the FPB Bus are mapped to 4 Kbyte boundaries. DS61143F-page 32 Preliminary © 2009 Microchip Technology Inc. ...

Page 35

TABLE 4-1: BUS MATRIX REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (1) BF88_2000 BMXCON 15:0 — — — 31:16 — — — BMX BF88_2010 (1) DKPBA 15:0 — — — ...

Page 36

TABLE 4-2: INTERRUPT REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 I2C1MIE I2C1SIE I2C1BIE BF88_1060 IEC0 15:0 INT3IE OC3IE IC3IE 31:16 — — — BF88_1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE 31:16 — — — ...

Page 37

TABLE 4-3: TIMER1-5 REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF80_0600 T1CON 15:0 ON FRZ SIDL 31:16 — — — BF80_0610 TMR1 15:0 31:16 — — — BF80_0620 PR1 15:0 ...

Page 38

TABLE 4-4: INPUT CAPTURE1-5 REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (1) BF80_2000 IC1CON 15:0 ON FRZ SIDL 31:16 BF80_2010 IC1BUF 15:0 31:16 — — — (1) BF80_2200 IC2CON 15:0 ...

Page 39

TABLE 4-5: OUTPUT COMPARE 1-5 REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 BF80_3220 OC2RS 15:0 31:16 — — — BF80_3400 OC3CON 15:0 ON FRZ SIDL 31:16 BF80_3410 OC3R 15:0 31:16 BF80_3420 OC3RS 15:0 ...

Page 40

TABLE 4-6: I2C1-2 REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF80_5050 I2C1TRN 15:0 — — — 31:16 — — — BF80_5260 I2C1RCV 15:0 — — — 31:16 — — ...

Page 41

TABLE 4-7: UART1-2 REGISTERS MAP (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (1) BF80_6210 U2STA 15:0 UTXISEL<1:0> UTXINV 31:16 — — — BF80_6220 U2TXREG 15:0 — — — 31:16 — — ...

Page 42

TABLE 4-9: ADC REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (1) BF80_9000 AD1CON1 15:0 ON FRZ SIDL 31:16 — — — (1) BF80_9010 AD1CON2 15:0 VCFG2 VCFG1 VCFG0 31:16 — ...

Page 43

TABLE 4-9: ADC REGISTERS MAP (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 BF80_9130 ADC1BUFC 15:0 31:16 BF80_9140 ADC1BUFD 15:0 31:16 BF80_9150 ADC1BUFE 15:0 31:16 BF80_9160 ADC1BUFF 15:0 Legend unknown value on Reset, ...

Page 44

TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_3060 DCH0CON 15:0 — — — 31:16 — — — BF88_3070 DCH0ECON 15:0 31:16 ...

Page 45

TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES (1) ONLY (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_3170 DCH1SSIZ 15:0 — — — 31:16 — — — BF88_3180 DCH1DSIZ ...

Page 46

TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES (1) ONLY (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_3280 DCH2CPTR 15:0 — — — 31:16 — — — BF88_3290 DCH2DAT ...

Page 47

TABLE 4-13: COMPARATOR REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF80_A000 CM1CON 15:0 ON COE CPOL 31:16 — — — BF80_A010 CM2CON 15:0 ON COE CPOL 31:16 — — — ...

Page 48

TABLE 4-16: SYSTEM CONTROL REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — BF80_F000 OSCCON 15:0 — COSC<2:0> 31:16 — — — BF80_F010 OSCTUN 15:0 — — — 31:16 — — — BF80_0000 ...

Page 49

TABLE 4-17: PORT A-G REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (4,5) BF88_6060 LATB 15:0 31:16 — — — (4,5) BF88_6070 ODCB 15:0 31:16 — — — BF88_6080 TRISC 15:0 ...

Page 50

TABLE 4-17: PORT A-G REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_6130 ODCE 15:0 — — — 31:16 — — — BF88_6140 TRISF (6) 15:0 — — TRISF13 31:16 — ...

Page 51

TABLE 4-18: CHANGE NOTICE AND PULL-UP REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_61D0 CNEN 15:0 31:16 — — — BF88_61E0 CNPUE 15:0 Legend unknown value on Reset, ...

Page 52

TABLE 4-21: PREFETCH REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — (1) BF88_4000 CHECON — — — 15:0 31:16 CHEWEN — — (1) BF88_4010 CHEACC 15:0 — — — LTAG — ...

Page 53

TABLE 4-22: RTCC REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 HR10<3:0> BF80_0220 RTCTIME 15:0 SEC10<3:0> 31:16 YEAR10<3:0> BF80_0230 RTCDATE 15:0 DAY10<3:0> 31:16 MIN10<3:0> BF80_0240 ALRMTIME 15:0 SEC10<3:0> 31:16 — — — BF80_0250 ...

Page 54

TABLE 4-25: USB REGISTERS MAP SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_5040 U1OTGIR 15:0 — — — 31:16 — — — BF88_5050 U1OTGIE 15:0 — — — 31:16 — — — ...

Page 55

TABLE 4-25: USB REGISTERS MAP (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_52A0 U1TOK 15:0 — — — 31:16 — — — BF88_52B0 U1SOF 15:0 — — — 31:16 — — ...

Page 56

TABLE 4-25: USB REGISTERS MAP (CONTINUED) SFR SFR Bits Bits Bits Virtual Name 31/15 30/14 29/13 Addr 31:16 — — — BF88_53A0 U1EP10 15:0 — — — 31:16 — — — BF88_53B0 U1EP11 15:0 — — — 31:16 — — ...

Page 57

... RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG meth- ods are described in the “PIC32MX3XX/4XX Program- ming Specification” (DS61145) document, which may be downloaded from the Microchip web site. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX an internal Preliminary ...

Page 58

... PIC32MX3XX/4XX NOTES: DS61143F-page 56 Preliminary © 2009 Microchip Technology Inc. ...

Page 59

... SYSTEM RESET BLOCK DIAGRAM MCLR Sleep or Idle WDT Voltage Time-out Regulator Enabled Rise DD Detect Configuration Mismatch Reset Software Reset © 2009 Microchip Technology Inc. PIC32MX3XX/4XX a detailed MCLR Glitch Filter WDTR POR Power-up Timer BOR Brown-out Reset CMR SWR Preliminary SYSRST DS61143F-page 57 ...

Page 60

... PIC32MX3XX/4XX NOTES: DS61143F-page 58 Preliminary © 2009 Microchip Technology Inc. ...

Page 61

... For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX3XX/4XX interrupts module includes the following features: • ...

Page 62

... IPC4<28:26> IPC4<25:24> IPC5<4:2> IPC5<1:0> IPC5<12:10> IPC5<9:8> IPC5<20:18> IPC5<17:16> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<20:18> IPC6<17:16> IPC6<28:26> IPC6<25:24> IPC7<4:2> IPC7<1:0> IPC7<12:10> IPC7<9:8> IPC7<20:18> IPC7<17:16> © 2009 Microchip Technology Inc. ...

Page 63

... Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See Table 1: “PIC32MX General Purpose – Features” and Table 2: “PIC32MX USB – Features” for available peripherals. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Vector IRQ Interrupt Bit Location ...

Page 64

... PIC32MX3XX/4XX NOTES: DS61143F-page 62 Preliminary © 2009 Microchip Technology Inc. ...

Page 65

... On-chip user-selectable divisor postscaler on select oscillator sources • Software-controllable switching between various clock sources • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • Dedicated on-chip PLL for USB peripheral © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143F-page 63 ...

Page 66

... USB Clock (48 MHz) UFRCEN Peripherals Postscaler div x PBCLK PBDIV<2:0> FRC CPU and Select Peripherals FRC /16 FRCDIV LPRC SOSC Clock Control Logic FSCM INT Fail-Safe Clock FSCM Event Monitor NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC © 2009 Microchip Technology Inc. ...

Page 67

... Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Pre-Fetch © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 9.1 Features • 16 Fully Associative Lockable Cache Lines • 16-byte Cache Lines • Cache Lines Allocated to Data • 2 Cache Lines with Address Mask to hold repeated instructions • ...

Page 68

... PIC32MX3XX/4XX NOTES: DS61143F-page 66 Preliminary © 2009 Microchip Technology Inc. ...

Page 69

... DMA BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus Address Decoder Global Control (DMACON) © 2009 Microchip Technology Inc. PIC32MX3XX/4XX • Fixed Priority Channel Arbitration • Flexible DMA Channel Operating Modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer ...

Page 70

... PIC32MX3XX/4XX NOTES: DS61143F-page 68 Preliminary © 2009 Microchip Technology Inc. ...

Page 71

... The register interface allows the CPU to communicate with the module. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX USB module includes the following features: • USB Full-Speed Support for Host and Device • Low-Speed Host Support • USB OTG Support • ...

Page 72

... To Clock Generator for Core and Peripherals USB Suspend Sleep or Idle USB Module USB Voltage Comparators SIE Transceiver Preliminary FRC Oscillator 8 MHz Typical (4) TUN<5:0> Div 2 (3) UFRCEN (6) FUPLLEN (7) 48 MHz USB Clock Registers and Control Interface DMA System RAM © 2009 Microchip Technology Inc. ...

Page 73

... Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX These functions depend on which peripheral features are on the device ...

Page 74

... REF module. Configuring the Comparator Reference mod- ule to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. Preliminary 0.3V (max 5. 0.03v 0.03v specification © 2009 Microchip Technology Inc. ...

Page 75

... SOSCO/T1CK SOSCEN SOSCI Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 13.1 Additional Supported Features • Selectable clock prescaler • Timer operation during CPU Idle and Sleep mode • ...

Page 76

... PIC32MX3XX/4XX NOTES: DS61143F-page 74 Preliminary © 2009 Microchip Technology Inc. ...

Page 77

... TGATE (TxCON<7>) (2) TxCK Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins not available on 64-pin devices. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Note: Throughout this chapter, references to registers TxCON, TMRx, and PRx use ‘x’ to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, ‘x’ represents Timer2 or 4 ...

Page 78

... Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5. 2: TxCK pins not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair. DS61143F-page 76 TMRx Sync LSHalfWord PRx Gate 1 0 Sync PBCLK 0 0 Preliminary TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) Prescaler 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) © 2009 Microchip Technology Inc. ...

Page 79

... INPUT CAPTURE BLOCK DIAGRAM ICx Input Prescaler Edge Detect ICM<2:0> ICFEDGE ICM<2:0> ICxCON © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes ...

Page 80

... PIC32MX3XX/4XX NOTES: DS61143F-page 78 Preliminary © 2009 Microchip Technology Inc. ...

Page 81

... The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX The following are some of the key features: • ...

Page 82

... PIC32MX3XX/4XX NOTES: DS61143F-page 80 Preliminary © 2009 Microchip Technology Inc. ...

Page 83

... Sync Control SSx/F SYNC SCKx Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Following are some of the key features of this module: • Master and Slave Modes Support • Four Different Clock Formats • Framed SPI Protocol Support • ...

Page 84

... PIC32MX3XX/4XX NOTES: DS61143F-page 82 Preliminary © 2009 Microchip Technology Inc. ...

Page 85

... Serial Clock Synchronization for I C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control). 2 • Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly. • Provides Support for Address Bit Masking. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX C) ” (DS61116 serial ...

Page 86

... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control PBCLK Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...

Page 87

... Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter © 2009 Microchip Technology Inc. PIC32MX3XX/4XX The primary features of the UART module are: • Full-duplex, 8-bit or 9-bit data transmission • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...

Page 88

... Character 1 to Transmit Shift Register TRMT bit DS61143F-page 86 bit 0 bit 1 bit 7/8 Character 1 UxTXIF Cleared by User bit 0 bit 1 bit 7/8 Character 1 Preliminary Stop bit Start bit bit 0 Stop bit Character 2 Character 2 to Transmit Shift Register © 2009 Microchip Technology Inc. ...

Page 89

... RIDLE bit Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Start bit 7 Stop ...

Page 90

... PIC32MX3XX/4XX NOTES: DS61143F-page 88 Preliminary © 2009 Microchip Technology Inc. ...

Page 91

... PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PIC32MX3XX/4XX Parallel Master Port Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Key features of the PMP module include: • 8-bit,16-bit interface • programmable address lines • ...

Page 92

... PIC32MX3XX/4XX NOTES: DS61143F-page 90 Preliminary © 2009 Microchip Technology Inc. ...

Page 93

... Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Following are some of the key features of this module: • Time: Hours, Minutes and Seconds • 24-Hour Format (Military Time) • Visibility of One-Half-Second Period • Provides Calendar: Weekday, Date, Month and Year • ...

Page 94

... PIC32MX3XX/4XX NOTES: DS61143F-page 92 Preliminary © 2009 Microchip Technology Inc. ...

Page 95

... inputs can be multiplexed with other analog inputs. REF REF © 2009 Microchip Technology Inc. PIC32MX3XX/4XX A block diagram of the 10-bit ADC is shown in Figure 22-1. The 10-bit ADC has 16 analog input pins, designated AN0-AN15. In addition, there are two ana- log input pins for external voltage reference connec- tions ...

Page 96

... PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143F-page 94 ADCS<7:0> 8 ADC Conversion Clock Multiplier 5,..., 512 Preliminary © 2009 Microchip Technology Inc. ADRC ...

Page 97

... On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. 3: Internally connected. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Following are some of the key features of this module: • Selectable inputs available include: - Analog inputs multiplexed with I/O pins ...

Page 98

... PIC32MX3XX/4XX NOTES: DS61143F-page 96 Preliminary © 2009 Microchip Technology Inc. ...

Page 99

... CVRSS = REF AV SS CVRSS = 0 © 2009 Microchip Technology Inc. PIC32MX3XX/4XX A block diagram of the module is shown in Figure 24-1. The resistor ladder is segmented to provide two ranges ) of voltage reference values and has a power-down func- tion to conserve power when the reference is not being used. The module’s supply reference can be provided from either device V ence ...

Page 100

... PIC32MX3XX/4XX NOTES: DS61143F-page 98 Preliminary © 2009 Microchip Technology Inc. ...

Page 101

... Peripherals continue to operate, but can option- ally be individually disabled. This is the lowest power mode for the device with a clock running. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX • Sleep Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted ...

Page 102

... CPU, the CPU will remain halted and the device will remain in Idle mode. • On any source of device Reset. • WDT time-out interrupt. See Section 26.2 “Watchdog Timer (WDT)” . Preliminary © 2009 Microchip Technology Inc. PBCLK divider ratio any timing calculation ...

Page 103

... Prevents boot and program Flash memory from being read or modified by an external programming device Protection disabled 0 = Protection enabled bit 27-25 Reserved: Write ‘ 1 ’ © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 26.1 Configuration Bits The Configuration bits can be programmed to select various device configurations. ...

Page 104

... PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘ 1 ’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘ 11 ’ if code-protect is enabled Debugger disabled 10 = Debugger enabled 01 = Reserved (same as ‘ 11 ’ setting Reserved (same as ‘ 11 ’ setting) DS61143F-page 102 Preliminary © 2009 Microchip Technology Inc. ...

Page 105

... All other combinations not shown result in operation = ‘ 10100 ’ © 2009 Microchip Technology Inc. PIC32MX3XX/4XX r-1 r-1 — — R/P-1 R/P-1 WDTPS<4:0> R/P-1 r-1 FPBDIV< ...

Page 106

... Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: Do not disable POSC (POSCMD = 00 ) when using this oscillator source. DS61143F-page 104 (1) Preliminary © 2009 Microchip Technology Inc. ...

Page 107

... Reserved: Write ‘ 1 ’ © 2009 Microchip Technology Inc. PIC32MX3XX/4XX r-1 r-1 r-1 — — — r-1 r-1 R/P-1 — ...

Page 108

... R/P-x R/P-x R/P-x USERID<15:8> R/P-x R/P-x R/P-x USERID<7:0> Programmable bit Preliminary © 2009 Microchip Technology Inc. r-1 r-1 — — bit 24 r-1 r-1 — — bit 16 R/P-x R/P-x bit 8 R/P-x R/P-x bit Reserved bit ...

Page 109

... W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-28 VER<3:0>: Revision Identifier bits bit 27-0 DEVID<27:0>: Device ID Note: See the PIC32MX Programming Specification for a list of Revision and Device ID values. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX DEVID<23:16> DEVID< ...

Page 110

... Section 28.0 “Electrical Characteristics” for more information on T Preliminary LPRC Control PWRT Enable PWRT Device Reset 0 1 NMI (Wake-up) Power Save disables the regulator pin. /V and V pins can be DDCORE CAP DD is applied PU at device start-up. See PWRT AND PWRT © 2009 Microchip Technology Inc. ...

Page 111

... SS (10 μF typ) Note 1: These are typical operating voltages. Refer to Section 28.1 “DC Characteristics” for the full operating ranges of V and V . DDCORE © 2009 Microchip Technology Inc. PIC32MX3XX/4XX 26.3.3 POWER-UP REQUIREMENTS is enabled, The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to ...

Page 112

... BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS PGEC1 PGED1 PGEC2 PGED2 TDI TDO TCK TMS TRCLK TRD0 TRD1 TRD2 TRD3 DS61143F-page 110 ICSP™ Controller ICESEL JTAG Controller JTAGEN DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> Preliminary Core © 2009 Microchip Technology Inc. ...

Page 113

... JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port bit 2 TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port bit 1-0 Reserved: Write ‘ 1 ’; ignore read © 2009 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — — — r-x ...

Page 114

... PIC32MX3XX/4XX NOTES: DS61143F-page 112 Preliminary © 2009 Microchip Technology Inc. ...

Page 115

... BGTZ Branch on Greater Than Zero Likely BGTZL Branch on Less Than or Equal to Zero BLEZ Note 1: This instruction is deprecated and should not be used. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Note: Refer to “MIPS32 grammers Volume II: The MIPS32 Instruction Set” at www.mips.com for more information. ...

Page 116

... HI = (int)Rs % (int) (uns)Rs / (uns) (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; Status if Status PC = ErrorEPC else PC = EPC Status Status ExtractField(Rs, pos, size InsertField(Rs, Rt, pos, size PC[31:28] || offset<<2 Preliminary Function = ERL = 0 EXL = 0 ERL © 2009 Microchip Technology Inc. ...

Page 117

... NOR Logical OR OR Logical OR Immediate ORI Read Hardware Register (if enabled by HWRE RDHWR Register) Note 1: This instruction is deprecated and should not be used. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Description GPR[31 PC[31:28] || offset<< Like JALR , but also clears execution and instruction hazards Like JR , but also clears execution and ...

Page 118

... NOP Rt = (int)Rs - (int) (uns)Rs - (uns)Rd Mem[Rs+offset Mem[Rs+offset Mem[Rs+offset Orders the cached coherent and uncached loads and stores for access to the shared memory SystemCallException TrapException (int)Immed TrapException Preliminary Function , Rd] PSS || Rt sa-1..0 31.. Rs-1..0 31.. bit mem[Rs+offset> bit © 2009 Microchip Technology Inc. ...

Page 119

... Write to GPR in Previous Shadow Set WRPGPR Word Swap Bytes Within Halfwords WSBH Exclusive OR XOR Exclusive OR Immediate XORI Note 1: This instruction is deprecated and should not be used. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Description if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < ...

Page 120

... PIC32MX3XX/4XX NOTES: DS61143F-page 118 Preliminary © 2009 Microchip Technology Inc. ...

Page 121

... Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2). © 2009 Microchip Technology Inc. PIC32MX3XX/4XX SS .................................................................................. -0.3V to +5.5V SS ...

Page 122

... Max. Frequency PIC32MX3XX/4XX 80 MHz (Note 1) Min. Typical Max. Unit -40 — +125 °C -40 — +85 ° INT θ (T – Max. Unit Notes 43 — °C — °C — °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A Units Conditions V/ms © 2009 Microchip Technology Inc. ...

Page 123

... Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40° ...

Page 124

... System clock is enabled and DLE . Preliminary ≤ +85°C for Industrial A Conditions 2.3V — 4 MHz 3.6V 2.3V 20 MHz, — (Note 3) 3.6V 2.3V 60 MHz — (Note 3) 3.6V 2.3V — 80 MHz 3.6V 2.3V LPRC (31 kHz) 3.3V (Note 3) 3.6V © 2009 Microchip Technology Inc. ...

Page 125

... Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at +70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...

Page 126

... V SMBus enabled, 2.3V ≤ V ≤ 5.5 PIN (Note 4) μ 3.3V PIN SS μ A ≤ V ≤ PIN DD Pin at high-impedance μ A ≤ V ≤ PIN DD Pin at high-impedance μ A ≤ V ≤ PIN DD μ A ≤ V ≤ PIN DD XT and HS modes © 2009 Microchip Technology Inc. ...

Page 127

... Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to PIC32MX Flash Programming Specification (DS61145) for operating conditions during programming and erase cycles. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ ...

Page 128

... Preliminary Comments ≤ +85°C for Industrial A Units Comments (Note 2) dB Max 1)V ICM DD (Note 2) nsec (Notes 1, 2) μ s Comparator module is configured before setting the comparator ON bit. (Note 2) ≤ +85°C for Industrial A Units Comments LSb LSb μ s © 2009 Microchip Technology Inc. ...

Page 129

... No. D320 V Regulator Output Voltage DDCORE D321 C External Filter Capacitor Value EFC D322 T PWRT © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40°C ≤ T ≤ +85°C for Industrial A Min. Typical Max. Units 1.62 1.80 1 ...

Page 130

... T Operating temperature (1) Min. Typical Max. Units — — — — 400 pF OS30 OS30 Preliminary -40°C ≤ T ≤ +85°C for Industrial A range ≤ +85°C for Industrial A Conditions EC mode C™ mode OS31 OS31 © 2009 Microchip Technology Inc. ...

Page 131

... MHz maximum for PIC32MX 40 MHz family variants. 4: PLL input requirements characterized, but tested at 10 MHz only at manufacturing. 5: This parameter is characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) Min. ...

Page 132

... T ≤ +85°C for Industrial A Min. Typical Max. Units -15 — +15 % changes. DD Preliminary ≤ +85°C for Industrial A Units Conditions 5 MHz ECPLL, HSPLL, XTPLL, FRCPLL modes MHz Measured over 100 ms period ≤ TA +85°C for industrial Conditions Conditions © 2009 Microchip Technology Inc. ...

Page 133

... T CNx High or Low Time (input) RBP Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX DI35 DI40 DO31 DO32 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40° ...

Page 134

... Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled DS61143F-page 132 SYSDLY SY02 CPU starts fetching code SY00 ( (Note SYSDLY SY02 CPU starts fetching code SY00 SY10 ( OST PU (Note DDCORE (T ) SYSDLY SY02 CPU starts fetching code SY01 (T ) PWRT (Note 1) < DDMIN Preliminary © 2009 Microchip Technology Inc. ...

Page 135

... MCLR SY30 T BOR Pulse Width (low) BOR Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX T MCLR (SY20) T BOR (T ) SYSDLY ...

Page 136

... Preliminary Tx20 (1) ≤ +85°C for Industrial A Conditions — nsec Must also meet parameter TA15. — nsec — nsec Must also meet parameter TA15. — nsec — nsec — nsec N = prescale value (1, 8, 64, 256) 100 kHz © 2009 Microchip Technology Inc. ...

Page 137

... IC11 T H ICx Input High Time CC IC15 T P ICx Input Period CC Note 1: These parameters are characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature (1) Min. [(12.5nsec 25nsec [(12 ...

Page 138

... Operating temperature (1) (2) Min Typical — — 50 — Preliminary ≤ +85°C for Industrial A Units Conditions nsec See parameter DO32. nsec See parameter DO31. -40°C ≤ T ≤ +85°C for Industrial A Max Units Conditions 25 nsec — nsec © 2009 Microchip Technology Inc. ...

Page 139

... The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX SP10 SP21 SP20 SP21 SP20 ...

Page 140

... T ≤ +85°Cfor Industrial A Max. Units Conditions — nsec — nsec — nsec See parameter DO32. nsec — See parameter DO31. nsec — See parameter DO32. nsec — See parameter DO31. nsec 15 — nsec — nsec © 2009 Microchip Technology Inc. ...

Page 141

... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI X SP40 Note: Refer to Figure 28-1 for load conditions © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) (2) Min. Typical — 10 SP70 SP72 SP73 SP72 ...

Page 142

... — — SCK Preliminary ≤ +85°C for Industrial A Units Conditions nsec nsec nsec nsec nsec See parameter DO32. nsec See parameter DO31. nsec nsec nsec nsec nsec nsec — © 2009 Microchip Technology Inc. ...

Page 143

... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 nsec. 4: Assumes 50 pF load on all SPIx pins. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX SP70 SP73 SP35 SP72 ...

Page 144

... Typical 60 — Output 5 — — SCK — — IM11 IM10 IM26 IM25 IM40 Preliminary -40°C ≤ T ≤ +85°C for Industrial A Max. Units Conditions — nsec 25 nsec — nsec nsec 25 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2009 Microchip Technology Inc. ...

Page 145

... Note 1: BRG is the value of the I C™ Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature (1) Min ...

Page 146

... IS26 IS25 IS40 Preliminary ≤ +85°C for Industrial A Conditions nsec — nsec — nsec — μ s The amount of time the bus must be free μ s before a new μ s transmission can start. pF IS34 Stop Condition IS21 IS33 IS45 © 2009 Microchip Technology Inc. ...

Page 147

... Stop Condition SU STO Setup Time Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ T Min. Max. 100 kHz mode 4.7 — ...

Page 148

... The amount of time the bus must be free before a new μ s transmission can start. μ ≤ +85°C for Industrial A Units Conditions (Note (Note 3) REFH DD – V (Note 1) V (Note 3) μ A ADC operating μ A ADC off V V © 2009 Microchip Technology Inc. ...

Page 149

... Note 1: These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A Min ...

Page 150

... AN 5.0 k Ω 2.5V to -40°C to 3.6V +85° 5.0 k Ω 2.5V to -40°C to 3.6V +85°C Preliminary ADC Channels Configuration REF REF SHA ADC REF REF SHA ADC REF REF REF ANx SHA ADC ANx REF © 2009 Microchip Technology Inc. ...

Page 151

... Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature (1) Min ...

Page 152

... Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One T for end of conversion. AD DS61143F-page 150 AD55 described in the “PIC32MX Family Reference Manual” (DS61132). SAMP Preliminary AD55 © 2009 Microchip Technology Inc. ...

Page 153

... Buffer( – Software sets ADxCON. ADON to start AD operation. 2 – Sampling starts after discharge period described in the “PIC32MX SAMP Family Reference Manual” (DS61132). 3 – Convert bit 9. 4 – Convert bit 8. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX AD55 AD55 – Convert bit 0. ...

Page 154

... Operating temperature -40°C ≤ T (1) Min. Typical Max. Units 20 — 20 — — — 0 — 25 — 25 — 25 — Preliminary PS7 PS1 PS2 ≤ +85°C for Industrial A Conditions — nsec — nsec 60 nsec 10 nsec — nsec — nsec — nsec © 2009 Microchip Technology Inc. ...

Page 155

... RD PM6 T PMRD or PMENB Active to Data In DSU Valid (data setup time) PM7 T PMRD or PMENB Inactive to Data In DHOLD Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Address Address<7:0> Address<7:0> PM2 PM3 PM1 Standard Operating Conditions: 2 ...

Page 156

... PM12 PM1 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ T (1) Min. Typical — — — Preliminary PM13 PM11 ≤ +85°C for Industrial A Max. Units Conditions — — — — — — © 2009 Microchip Technology Inc. ...

Page 157

... These parameters are characterized, but not tested in manufacturing. FIGURE 28-23: EJTAG TIMING CHARACTERISTICS TCK TMS TDI T TDO TRST* T TRST*low T rf © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ T (1) Min. Typ 3.0 — — — 2.0 — ...

Page 158

... Operating temperature -40°C ≤ T (1) Min. Max. Units 25 — nsec 10 — nsec 10 — nsec 5 — nsec 3 — nsec — 5 nsec — 5 nsec 25 — nsec — — nsec Preliminary ≤ +85°C for Industrial A Conditions © 2009 Microchip Technology Inc. ...

Page 159

... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Example PIC32MX360F 512L-80I/PT ...

Page 160

... PIC32MX3XX/4XX 29.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH NOTE 1 c β 1RWHV DS61143F-page 158 [ [ PP %RG NOTE 2 A φ Preliminary PP >74)3@ α A2 © 2009 Microchip Technology Inc. ...

Page 161

... Microchip Technology Inc. PIC32MX3XX/4XX [ [ PP %RG\ PP >74)3@ Preliminary DS61143F-page 159 ...

Page 162

... PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143F-page 160 Preliminary © 2009 Microchip Technology Inc. ...

Page 163

... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143F-page 161 ...

Page 164

... PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143F-page 162 Preliminary © 2009 Microchip Technology Inc. ...

Page 165

... NOTE 1 c β 1RWHV © 2009 Microchip Technology Inc. PIC32MX3XX/4XX [ [ PP %RG NOTE 2 A φ Preliminary PP >74)3@ α A2 DS61143F-page 163 ...

Page 166

... PIC32MX3XX/4XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH DS61143F-page 164 [ [ PP %RG\ Preliminary © 2009 Microchip Technology Inc. PP >74)3@ ...

Page 167

... Section 4.0 “Memory Organization” Section 7.0 “Interrupt Controller” Section 12.0 “I/O Ports” Section 26.0 “Special Features” © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Revision F (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. ...

Page 168

... Replaced Table 28-24. Replaced Table 28-25. Updated Table 28-36. “Package Marking Information” . Added the 64-Lead QFN (MR) package drawing and land pattern to Section 29.2 “Package Details” . Added the MR package designator for the 64-Lead (9x9x0.9) QFN. Preliminary © 2009 Microchip Technology Inc. ...

Page 169

... I/O Ports 71 85 Parallel I/O (PIO Packaging 157 Details 158 Marking 157 PIC32 Family USB Interface Diagram 70 © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Pinout I/O Descriptions (table) 12 Power-on Reset (POR) and On-Chip Voltage Regulator 109 S Serial Peripheral Interface (SPI) 57 Special Features 101 ...

Page 170

... PIC32MX3XX/4XX NOTES: DS61143F-page 168 Preliminary © 2009 Microchip Technology Inc. ...

Page 171

... TQFP (Thin Quad Flatpack 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise Engineering Sample © 2009 Microchip Technology Inc. PIC32MX3XX/4XX Examples: PIC32MX320F032H-40I/PT: General purpose PIC32MX program memory, 64-pin, Industrial temp., TQFP package. ...

Page 172

... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...