PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet
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... PIC32MX3XX/4XX Family 64/100-Pin General Purpose and USB © 2008 Microchip Technology Inc. Data Sheet 32-Bit Flash Microcontrollers Preliminary DS61143C ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MIPS standard enhanced JTAG interface • Unintrusive Hardware-Based Instruction Trace • IEEE Std 1149.2 Compatible (JTAG) Boundary Scan © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Analog Features: • 16-Channel 10-Bit Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep, Idle • ...
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... PIC32MX360F256L 100 256/32 PIC32MX360F512L 100 512/32 Program /Data Device Pins Memory (KB) PIC32MX420F032H 64 32/8 PIC32MX440F256H 64 256/32 PIC32MX440F128L 100 128/32 PIC32MX460F256L 100 256/32 PIC32MX460F512L 100 512/32 DS61143C-page 2 General Purpose Timers/C apture/ Compare 5/5/5 0 Yes Yes No 5/5/5 0 Yes Yes No 5/5/5 0 Yes Yes No 5/5/5 4 ...
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... Pin Diagram (64-Pin General Purpose) 64-Pin TQFP (General Purpose) PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 V V C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/V -/CV -/CN3/RB1 REF REF PGD1/EMUD1/PMA6/AN0/V +/CV +/CN2/RB0 REF REF © 2008 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX3XXH Preliminary 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 ...
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... C1IN+/AN5/CN7/RB5 20 C1IN-/AN4/CN6/RB4 21 C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/SS1/CN4/RB2 23 PGC1/EMUC1/AN1/CN3/RB1 24 PGD1/EMUD1/AN0/CN2/RB0 25 DS61143C-page PIC32MX3XXL Preliminary © 2008 Microchip Technology Inc SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 ...
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... Pin Diagram (64-pin USB) 64-Pin TQFP (USB) PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGC1/EMUC1/AN1/V -/CV -/CN3/RB1 REF REF PGD1/EMUD1/PMA6/AN0/V +/CV +/CN2/RB0 REF REF © 2008 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX4XXH Preliminary 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 IC4/PMCS1/PMA14/INT4/RD11 ...
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... VBUSON/C1IN+/AN5/CN7/RB5 20 C1IN-/AN4/CN6/RB4 21 C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/CN4/RB2 23 PGC1/EMUC1/AN1/CN3/RB1 24 PGD1/EMUD1/AN0/CN2/RB0 25 DS61143C-page PIC32MX4XXL Preliminary © 2008 Microchip Technology Inc SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 IC3/SCKI/PMCS2/PMA15/RD10 IC2/SS1/RD9 IC1/RTCC/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3 ...
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... Special Features ...................................................................................................................................................................... 555 28.0 Programming and Diagnostics ................................................................................................................................................. 567 29.0 Development Support............................................................................................................................................................... 579 30.0 Electrical Characteristics .......................................................................................................................................................... 583 30.3 AC Electrical Specifications...................................................................................................................................................... 614 31.0 Packaging Information.............................................................................................................................................................. 619 Index ................................................................................................................................................................................................. 627 World Wide Sales and Service .......................................................................................................................................................... 630 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS61143C-page 8 Preliminary © 2008 Microchip Technology Inc. ...
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... PIC32MX360F512L • PIC32MX420F032H • PIC32MX440F256H • PIC32MX440F128L • PIC32MX460F256L • PIC32MX460F512L This family introduces a new line of Microchip devices: a 32-bit RISC microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC32MX3XX/4XX family offers a new migration option for those high-performance appli- cations which may be outgrowing their 16-bit platforms ...
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... Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. DS61143C-page 10 Preliminary © 2008 Microchip Technology Inc. ...
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... Hardware Break Points 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Internal LDO Resets (and delays) POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit Mismatch) Instruction Support Packages © 2008 Microchip Technology Inc. PIC32MX3XX/4XX DC – 80 MHz 64K 128K 256K 16K 16K 32K ...
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... Yes POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit Mismatch) (PWRT, OST, PLL Lock) MIPS32 Enhanced Architecture (Release 2) MIPS16e™ Code Compression 64-pin TQFP Preliminary 256K 512K 32K 32K Ports USB 22 2 Yes 100-pin TQFP © 2008 Microchip Technology Inc. ...
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... Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-3 for I/O port pin descriptions. 2: Some features are not available on certain devices. 3: BOR functionality is provided when the on-board voltage regulator is enabled. 4: PORTA is not present on 64-pin devices © 2008 Microchip Technology Inc. PIC32MX3XX/4XX V DDCORE ...
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... Peripheral Bridge (1) Data RAM Timer3 Timer4 Timer5 Preliminary /V CAP Power- Timer MCLR (1) Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out (2) Reset CN1-22 (1) PWM OC 1 1,5 (1) SPI 1,2 I2C 1 (1) PMP UART 1,2 Comparators RTCC 10-bit ADC © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... Comparator Voltage Reference Output Enable for On-Chip Voltage Regulator Input Capture Inputs External Interrupt Inputs Master Clear (Device Reset) Input. Bring this line low to cause a Reset Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... Parallel Master Port Read Strobe (Master Mode 2) O — Parallel Master Port Read/Write Strobe (Master Mode 1). O — Parallel Master Port Write Strobe (Master Mode Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... PORTE Digital I/O. I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST PORTF Digital I/O. I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... Positive Supply for Microcontroller Core Logic (regulator disabled). I ANA A/D Reference Voltage (Low) Input. I ANA A/D Reference Voltage (High) Input. P — Ground Reference for Logic and I/O pins Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... USB D+ I/O ANA USB Enable for On-Chip Voltage Regulator Input Capture Inputs External Interrupt Inputs Master Clear (Device Reset) Input. Bring this line low to cause a Reset Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... Parallel Master Port Read Strobe (Master mode 2) O — Parallel Master Port Read/Write Strobe (Master mode 1) O — Parallel Master Port Write Strobe (Master mode Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... I/O ST I/O ST PORTE Digital I/O. I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST PORTF Digital I/O. I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). Multiplexed peripheral inputs have no priority. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Input ...
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... Ground Reference for Logic and I/O pins. I ANA USB Bus Power Monitor P — USB Internal Transceiver Supply O — USB Host and OTG Bus Power Control Output I ST USB OTG ID Detect ST = Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency © 2008 Microchip Technology Inc. PIC32MX3XX/4XX • Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide ...
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... MIPS16e support • Enhanced JTAG (EJTAG) Controller FIGURE 2-1: MCU BLOCK DIAGRAM MDU Execution Core (RF/ALU/Shift) System Coprocessor DS61143C-page 32 EJTAG Trace TAP Debug I/F FMT Bus Interface Dual Bus I/F Power Mgmt Preliminary Trace I/F Off-Chip © 2008 Microchip Technology Inc. ...
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... Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and Store Aligner © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 2.2.2 MULTIPLY/DIVIDE UNIT (MDU) The PIC32MX3XX/4XX family core includes a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations ...
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... HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. DS61143C-page 34 Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits of Preliminary Latency Repeat Rate © 2008 Microchip Technology Inc. ...
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... Program counter at last debug exception 25-29 Reserved Reserved in the PIC32MX3XX/4XX family core (1) 30 ErrorEPC Program counter at last error (2) 31 DESAVE Debug handler scratchpad register Note 1: Registers used in exception processing. 2: Registers used during debug. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX or disabled. Preliminary DS61143C-page 35 ...
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... EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) AdEL Load address alignment error Load reference to protected address AdES Store address alignment error Store to protected address DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare DS61143C-page 36 Description Preliminary © 2008 Microchip Technology Inc. ...
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... The interrupt controller specifies which shadow set should be used upon entry to a particular vector. The shadow registers further improve interrupt latency by avoiding the need to save context when invoking an interrupt handler. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 2.2.5 GPR SHADOW REGISTERS Release 2 of the MIPS32 Architecture optionally ...
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... Note 1: This space is mapped to memory in user or kernel mode, and by the EJTAG module in Debug mode. DS61143C-page 38 Fixed Mapped (1) kseg3 Memory/EJTAG Fixed Mapped kseg2 Fixed Mapped, 512 MB kseg1 Unmapped, 512 MB Uncached kseg0 Unmapped, 512 MB kuseg Fixed Mapped, 2048 MB Preliminary © 2008 Microchip Technology Inc. ...
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... Table 2-5 shows how the cacheability of the virtual address segments is controlled by these fields. TABLE 2-4: CACHE COHERENCY ATTRIBUTES Config Register Fields Cache Coherency Attribute K23, KU, and K0 2 Uncached 3 Cacheable © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Virtual Physical Address Address SRAM FMT Interface Physical Virtual Address Address ...
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... Controlled by the K23 field (bits 30:28) of the Config register. See Figure 2-4 for mapping. Controlled by the K23 field (bits 30:28) of the Config register. See Figure 2-4 for mapping THE PIC32MX3XX/4XX FAMILY CORE 0 Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000 useg/kuseg 0x4000_0000 reserved 0x2000_0000 kseg0/kseg1 0x0000_0000 Preliminary © 2008 Microchip Technology Inc. ...
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... I and D requests which are then serviced in parallel. The internal buses are connected to the Bus Matrix unit, which is a switch fabric that provides this parallel operation. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 0xE000_0000 0xC000_0000 0x8000_0000 0x0000_0000 2.3.3 MIPS16E EXECUTION ...
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... The trace information is collected in an off-chip memory, for regeneration software. Off-chip trace memory is accessed through a special trace probe that consists of 4 data pins plus a clock. Preliminary types of simple hardware implemented in the occur on instruction fetch post-capture processing by trace © 2008 Microchip Technology Inc. ...
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... MCU if desired. 2.7 I/O Pin Configuration The MCU module has EJTAG pins that may be config- ured as user-available I/O pins. If EJTAG is used for debug important to make sure that software does not clear DDPCON<JTAGEN>. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 43 ...
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... PIC32MX3XX/4XX NOTES: DS61143C-page 44 Preliminary © 2008 Microchip Technology Inc. ...
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... Branch on Greater Than or Equal To Zero Likely BGEZL Branch on Greater Than Zero BGTZ Branch on Greater Than Zero Likely BGTZL Branch on Less Than or Equal to Zero BLEZ © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Table 3-1 provides implemented by the PIC32MX3XX/4XX family family core. Description Immed ...
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... Rt = Status; Status LO = (int)Rs / (int) (int)Rs % (int) (uns)Rs / (uns) (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; Status if SR[2> ErrorEPC else PC = EPC SR[1> SR[2> ExtractField(Rs, pos, size InsertField(Rs, Rt, pos, size PC[31:28> || offset<<2 Preliminary Function = © 2008 Microchip Technology Inc. ...
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... MUL Integer Multiply MULT Unsigned Multiply MULTU No Operation NOP (Assembler idiom for: SLL r0, r0, r0) Logical NOR NOR Logical OR OR © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Description GPR[31> PC[31:28> || offset<< Like JALR, but also clears execution and instruction hazards Like JR, but also clears execution and ...
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... Rd = (int)Rt >> Rs[4:0> (uns)Rt >> (uns)Rt >> Rs[4:0> NOP Rt = (int)Rs - (int) (uns)Rs - (uns)Rd Mem[Rs+offset> See Architecture Reference Manual See Architecture Reference Manual See Software User’s Manual SystemCallException Preliminary Function , Rd> PSS || Rt sa-1..0 31.. Rs-1..0 31..Rs mem[Rs+offset> © 2008 Microchip Technology Inc. ...
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... WRPGPR Word Swap Bytes Within Halfwords WSBH Exclusive OR XOR Exclusive OR Immediate XORI Zero-extend byte (MIPS16e™ only) ZEB Zero-extend half (MIPS16e only) ZEH © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Description TrapException (int)Immed TrapException if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs > ...
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... PIC32MX3XX/4XX NOTES: DS61143C-page 50 Preliminary © 2008 Microchip Technology Inc. ...
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... Software-controllable switching between various clock sources • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown A simplified diagram of the oscillator system is shown in Figure 4-1. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 51 ...
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... FRC /16 div 16 FRCDIV LPRC SOSC Preliminary USB Clock (48 MHz) Peripherals Postscaler PBCLK div x PBDIV<2:0> CPU & Select Peripherals Clock Control Logic Fail-Safe FSCM INT Clock Monitor FSCM Event NOSC<2:0> COSC<2:0> OSWEN FSCMEN<1:0> WDT, PWRT Timer1, RTCC © 2008 Microchip Technology Inc. ...
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... FCKSM<1:0> 7:0 IESO Note 1: FUPLLEN and FPLLODIV<2:0> are only available on PIC32MX4XX family variants. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX The Oscillator module also has the following associated bits for interrupt control: • Interrupt Flag Status bits (IFS1<14>) for Clock Fail FSCMIF in IFS1 Interrupt register • ...
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... DS61143C-page 54 Bit Bit Bit Bit 28/20/12/ 27/19/11/ 30/22/14/6 29/21/13/5 4 — — — — — — — — (1) — — — — FPLLMULT<2:0> — Preliminary Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 3 — — — FPLLODIV<2:0> (1) FUPLLIDIV<2:0> FPLLIDIV<2:0> © 2008 Microchip Technology Inc. ...
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... SOSCRDY: Secondary Oscillator Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary oscillator is either turned off or is still warming up bit 21 Reserved: Maintain as ‘0’; ignore read © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-x R/W-x R/W-0 PLLODIV<2:0> R/W-x ...
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... Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled bit 5 LOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled DS61143C-page 56 Preliminary © 2008 Microchip Technology Inc. ...
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... Enable Secondary Oscillator 0 = Disable Secondary Oscillator Note: On Reset these bits are set to the value of the FSOSCEN Configuration bit DEVCFG1<5> bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 57 ...
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... R/W-0 R/W-0 R/W-0 TUN<5:0> Programmable bit Preliminary r-x r-x — — bit 24 r-x r-x — — bit 16 r-x r-x — — bit 8 R/W-0 R/W-0 bit Reserved bit © 2008 Microchip Technology Inc. ...
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... A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or by software. 2: The LPRC oscillator will automatically be enabled when this bit is set. Note: Shaded bit names in this Interrupt register control other PIC32MX3XX/4XX peripherals and are not related to the oscillator. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — ...
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... R/W-0 R/W-0 I2C2SIF I2C2BIF U2TXIF R/W-0 R/W-0 R/W-0 CMP2IF CMP1IF PMPIF P = Programmable bit Preliminary R/W-0 R/W-0 USBIF FCEIF bit 24 R/W-0 R/W-0 DMA1IF DMA0IF bit 16 R/W-0 R/W-0 U2RXIF U2EIF bit 8 R/W-0 R/W-0 AD1IF CNIF bit Reserved bit © 2008 Microchip Technology Inc. ...
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... Bit Value at POR: (‘0’, ‘1’ Unknown) bit 14 FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note: Shaded bit names in this Interrupt register control other PIC32MX3XX/4XX peripherals and are not related to the oscillator. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — — ...
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... R/W-0 R/W-0 DMA0IP<2:0> R/W-0 R/W-0 R/W-0 RTCCIP<2:0> R/W-0 R/W-0 R/W-0 FSCMIP<2:0> R/W-0 R/W-0 R/W-0 I2C2IP<2:0> Programmable bit Preliminary R/W-0 R/W-0 DMA0IS<1:0> bit 24 R/W-0 R/W-0 RTCCIS<1:0> bit 16 R/W-0 R/W-0 FSCMIS<1:0> bit 8 R/W-0 R/W-0 I2C2IS<1:0> bit Reserved bit © 2008 Microchip Technology Inc. ...
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... Internal External Clock Switchover mode enabled; Two-Speed Start-up mode 0 = Internal External Clock Switchover mode disabled; Single-Speed Start-up mode bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-1 r-1 r-1 — — ...
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... FRC Divided by 16 (FRCDIV16) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, or ECPLL) 010 = Primary Oscillator without PLL (XT, HS, or EC) 001 = Fast RC Oscillator with PLL 000 = Fast RC Oscillator (FRC) DS61143C-page 64 Preliminary © 2008 Microchip Technology Inc. ...
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... FPLLMULT<2:0>: Default PLL Multiplier Value bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-1 r-1 r-1 — — — r-1 ...
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... DEVCFG2 BOOT CONFIGURATION REGISTER bit 2-0 FPLLIDIV<2:0>: Default PLL Input Divider Value bits 111 = Divide by 12 110 = Divide by 10 101 = Divide by 6 100 = Divide by 5 011 = Divide by 4 010 = Divide by 3 001 = Divide by 2 000 = Divide by 1 DS61143C-page 66 Preliminary © 2008 Microchip Technology Inc. ...
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... In this mode, the PLL input divider is forced to ‘2’ to provide a 4 MHz input to the PLL. This parameter cannot be modified and satisfies the requirements described in Note 3. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX • Internal Low-Power RC Oscillator (LPRC) Each of the clock sources has unique configurable options, such as a PLL, input divider, and/or output divider, that are detailed in their respective sections ...
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... Figure 4-3). Note: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. Preliminary © 2008 Microchip Technology Inc. FNOSC2: Notes FNOSC0 1,4 001 1 ...
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... PBCLK OSCO (Clock Out) FIGURE 4-4: EXTERNAL CLOCK INPUT OPERATION WITH NO CLOCK-OUT (EC, ECPLL MODE) Clock from OSCI Ext. System PIC32MX3XX/4XX I/O I/O (OSCO) © 2008 Microchip Technology Inc. PIC32MX3XX/4XX To Internal Logic OSCI XTAL Enable ( OSCO S (1) R PIC32MX3XX/4XX , is typically in the range MΩ. ...
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... After the PLL has achieved a lock or the PLL start-up timer has expired, the bit is set. The bit will be set upon the expiration of the timer even if the PLL has not achieved a lock. Preliminary System Clock Phase Locked Loop (PLL) © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC32MX3XX/4XX PLLODIV PLLMULT Multiplier Postscaler <2:0> <2:0> 16 ‘000’ ‘000’ 15 ‘001’ ‘000’ ‘010’ ‘000’ ‘011’ ‘000’ ‘100’ ‘000’ ‘101’ ...
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... Returning to the faster main oscillator will still require an oscillator start-up time crystal type source and/or uses the PLL. In addition, the oscillator will need to remain running at all times for Real-Time Clock applications and may be required for Timer1. Preliminary © 2008 Microchip Technology Inc. ...
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... MHz input to the PLL. This parameter cannot be modified. The desired PLL multiplier and output divider values can be chosen to provide the desired device frequency © 2008 Microchip Technology Inc. PIC32MX3XX/4XX // ensure OSCCON is locked // Write Key1 to SYSKEY // Write Key2 to SYSKEY ...
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... The ULOCK bit is cleared at a Power-on Reset. It remains clear when any clock source not using the PLL is selected. Refer to the Electrical Characteristics section in the specific device data sheet for further information on the USB PLL lock interval. Preliminary . If the PLL ULOCK © 2008 Microchip Technology Inc. ...
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... FSCMIP<2:0> (IPC8<12:10>) and subpriority (IPC8<9:8>). The clock source will remain FRC until a © 2008 Microchip Technology Inc. PIC32MX3XX/4XX device Reset or a clock switch is performed. Failure to enable the FSCM interrupt will not inhibit the actual clock switch. The FSCM module takes the following actions when switching to the FRC oscillator: 1 ...
Page 78
... The clock switching hardware compares the COSC<2:0> Status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this Preliminary read the COSC<2:0> bits © 2008 Microchip Technology Inc. ...
Page 79
... The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 4-2. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 4.2.6.3 Clock Switching Considerations When incorporating clock switching into an application, users should keep certain things in mind when designing their code ...
Page 80
... COSC<2:0>, POSCMD COSC<2:0>, POSCMD, OSCOFNC COSC<2:0>, POSCMD, OSCOFNC COSC<2:0>, POSCMD, OSCOFNC COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> COSC<2:0> Preliminary (1) TRIS Pin Type X OSC X OSC LOCK N X PBCLK NPUT NPUT O O UTPUT UTPUT X GPIO X GPIO X GPIO X GPIO X OSC X OSC © 2008 Microchip Technology Inc. ...
Page 81
... OSCO is turned off to save current. 4.3.2 SOSCI AND SOCI PIN FUNCTIONS IN NON-EXTERNAL OSCILLATOR MODES When the secondary oscillator (SOSC) on SOSCI and SOSCO pin is not configured as a clock source the pins are automatically reconfigured as a digital I/O. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 79 ...
Page 82
... PIC32MX3XX/4XX NOTES: DS61143C-page 80 Preliminary © 2008 Microchip Technology Inc. ...
Page 83
... FIGURE 5-1: SYSTEM RESET BLOCK DIAGRAM MCLR SLEEP or IDLE Voltage Time-out Regulator Enabled Rise DD Detect Configuration Mismatch Reset Software Reset © 2008 Microchip Technology Inc. PIC32MX3XX/4XX MCLR Glitch Filter WDTR WDT POR Power-up Timer BOR Brown-out Reset CMR SWR Preliminary SYSRST DS61143C-page 81 ...
Page 84
... Write inverts selected bits in RSWRST, read yields undefined value Preliminary Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 — — — — — — — CMR VREGS IDLE BOR POR — — — — — — — — — — — SWRST © 2008 Microchip Technology Inc. ...
Page 85
... Note 1: User must clear this bit to view next detection. 2: BOR is also set after a Power-on Reset. 3: The RCON flag bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX (3) r-x ...
Page 86
... Note 1: User must clear this bit to view next detection. 2: BOR is also set after a Power-on Reset. 3: The RCON flag bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. DS61143C-page 84 (3) (CONTINUED) (1)(2) (1) Preliminary © 2008 Microchip Technology Inc. ...
Page 87
... SWRST: Software Reset Trigger bit 1 = Enable software reset event Note: The system unlock sequence must be performed before the SWRST bit can be written. A read must follow the write of this bit to generate a Reset. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — ...
Page 88
... Reset event occurs recom- mended that 4 ‘NOP’ instructions or a “while(1);” state- ment be placed after the READ instruction. . The SWR Status bit (RCON<6>) is set to indicate the POR Software Reset. DD rise rate speci- Preliminary © 2008 Microchip Technology Inc. ...
Page 89
... Configuration bit values are not found opposite to each other, a Configuration Mismatch event is generated which causes a device Reset device Reset occurs as a result of a Configuration Mismatch, the CM bit (RCON<9>) is set. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 5.3 Reset States 5.3.1 ...
Page 90
... RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. DS61143C-page 88 Program Counter 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 1 u 0xBFC0_0000 1 u 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 0xBFC0_0000 (1) Vector (1) Vector Preliminary ( ( ( ( ( ( © 2008 Microchip Technology Inc. ...
Page 91
... Fail-Safe Clock Monitor delay. FSCM 7: Included is a required delay of 8 system clock cycles before the Reset to the CPU core is deasserted. 5.5 Interrupts There are no interrupts for this module. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Set by: POR POR, BOR MCLR Reset Software Reset Command ...
Page 92
... PIC32MX3XX/4XX NOTES: DS61143C-page 90 Preliminary © 2008 Microchip Technology Inc. ...
Page 93
... Robust bus exception handling to intercept runaway code. • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable and non-cacheable address regions © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 6.1 PIC32MX3XX/4XX Memory Layout PIC32MX3XX/4XX microcontrollers implement two address spaces: Virtual and Physical. All hardware ...
Page 94
... Partition) Internal Flash (User Partition) Reserved Reserved Reserved Internal Boot Flash Internal Peripherals Partition) Internal Program Flash Partition) Reserved Reserved Internal RAM Preliminary 0xFFFFFFFF 0xBF000000 + BMXDUDBA 0xBD000000 + BMXPUPBA 0x4FFFFFFF 0x40000000 0x1FC00000 0x1F800000 0x1D000000 0x0FFFFFFF BMXDUDBA 0x00000000 © 2008 Microchip Technology Inc. ...
Page 95
... BMXPUPBA 31:24 — 23:16 — 15:8 7:0 BF88_2048 BMXPFMSZ 31:24 23:16 15:8 7:0 BF88_204C BMXBOOTSZ 31:24 23:16 15:8 7:0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 — — — — — — BMXERRIXI BMXERRICD — ...
Page 96
... R/W-0 — — Programmable bit Preliminary r-x r-x — — bit 24 R/W-1 R/W-1 BMX- BMXERRIS ERRDS bit 16 r-x r-x — — bit 8 R/W-0 R/W-0 BMXARB<2:0> bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 97
... Reserved: Maintain as ‘0’; ignore read bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111...011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 000 = Arbitration Mode 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 95 ...
Page 98
... R/W-0 R/W-0 R-0 BMXDKPBA<15:8> R-0 R-0 R-0 BMXDKPBA<7:0> Programmable bit Preliminary r-x r-x — — bit 24 r-x r-x — — bit 16 R-0 R-0 bit 8 R-0 R-0 bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 99
... When non-zero, the value selects the relative base address for User mode data space in RAM Note: If non-zero, the value must be greater than BMXDKPBA. bit 10-0 BMXDUDBA<10:0>: Read-Only bits Value is always ‘0’, which forces 2 KB increments © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — ...
Page 100
... R/W-0 R/W-0 R-0 BMXDUPBA<15:8> R-0 R-0 R-0 BMXDUPBA<7:0> Programmable bit Preliminary r-x r-x — — bit 24 r-x r-x — — bit 16 R-0 R-0 bit 8 R-0 R-0 bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 101
... BMXDRMSZ: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00002000 = device has 8 KB RAM 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM © 2008 Microchip Technology Inc. PIC32MX3XX/4XX BMXDRMSZ<31:24> ...
Page 102
... R/W-0 R/W-0 — BMXPUPBA<19:16> R/W-0 R/W-0 R-0 BMXPUPBA<15:8> R-0 R-0 R-0 BMXPUPBA<7:0> Programmable bit Preliminary r-x r-x — — bit 24 R/W-0 R/W-0 bit 16 R-0 R-0 bit 8 R-0 R-0 bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 103
... Static value that indicates the size of the PFM in bytes: 0x00008000 = device has 32 KB Flash 0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash 0x00040000 = device has 256 KB Flash 0x00080000 = device has 512 KB Flash © 2008 Microchip Technology Inc. PIC32MX3XX/4XX BMXPFMSZ<31:24> ...
Page 104
... BMXBOOTSZ: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00003000 = device has 12 KB boot Flash DS61143C-page 102 BMXBOOTSZ<31:24> BMXBOOTSZ<23:16> BMXBOOTSZ<15:8> BMXBOOTSZ<7:0> Programmable bit Preliminary R R bit bit bit bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 105
... FIGURE 6-2: USER/KERNEL ADDRESS SEGMENTS 0xFFFFFFFF KERNEL SEGMENTS (KSEG 0,1,2,3) 0x80000000 0x7FFFFFFF USER / KERNEL SEGMENT (USEG / KUSEG) 0x00000000 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 103 ...
Page 106
... Size in Bytes End Address Calculation 0x1FC02FFF 12 KB 0x1D00000 + BMXPUPBA BMXPUPBA - 1 0x1D000000 + BMXPUPBA BMXPUPBA - 1 BMXDKPBA - 1 BMXDKPBA BMXDUDBA -1 BMXDUDBA - BMXDKPBA 0x1F8FFFFF 1 MB 0xBD000000 + PFM Size - PFM Size - 1 BMXPUPBA 0xBF000000 + BMXDUPBA - BMXDUPBA - 1 BMXDUDBA 0xBF000000 + DRM Size - (3) RAM Size - 1 BMXDUPBA © 2008 Microchip Technology Inc. ...
Page 107
... PFMWS (CHECON<2:0>) is one less. For example, core clock frequency is 72 MHz. The number of Wait states will be 72/20 = 3.6, i.e., 3 Wait states. Therefore the actual value written to PFMWS bits will be 2. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 6.6 Program Flash Memory Partitioning The Program Flash Memory can be partitioned for User and Kernel mode programs as shown in Figure 6-3 ...
Page 108
... RAM, please refer to the Memory Organization section of the PIC32MX3XX/4XX Family Reference Manual (DS61132). DS61143C-page 106 Physical Address Flash Partition for Kernel Program (KSEG 0/1) 0x1D000000 Optional Flash Partition for User Program (USEG/KUSEG) 0xBD000000+ BMXPUPBA ‘0’ , then: Preliminary © 2008 Microchip Technology Inc. ...
Page 109
... KSEG0 that are available to the CPU when it is operating in Kernel mode. Table 6-5 shows the address map for system resources mapped in KSEG1 that are available to the CPU when it is operating in Kernel mode. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Physical Address 0x00000000 +BMXDUDBA ...
Page 110
... User Data DRM DRM User Program User Program User Program DRM=8KB DRM=16KB DRM=16KB DRM=16KB RSVD DRM=32KB DRM=32KB RSVD Preliminary © 2008 Microchip Technology Inc. RSVD RSVD PFM PFM User Program RSVD RSVD DRM DRM User Data DRM DRM User Program DRM=32KB ...
Page 111
... Test Flash 0x9FFF_FFFF 0x1FFF_FFFF Note 1: Not available in KSEG0 if mapped to USEG/KUSEG (i.e. BMXDUDBA or BMXDUPBA non-zero). 2: Not available in KSEG0 if mapped in USEG/KUSEG (i.e. BMXPUPBA non-zero). © 2008 Microchip Technology Inc. PIC32MX3XX/4XX DRM DRM Kernel Data Kernel Data Kernel Data DRM DRM ...
Page 112
... Peripherals Peripherals Peripherals RSVD RSVD Boot Flash Boot Flash Boot Flash RSVD RSVD Test Flash Test Flash Test Flash Preliminary © 2008 Microchip Technology Inc. DRM DRM Kernel Data DRM DRM Kernel Program Note 1 Note 1 DRM=32KB RSVD RSVD PFM PFM Kernel Program ...
Page 113
... Configuration BF80_F200 Flash (NVM) BF80_F400 Reset BF80_F600 Interrupts BF88_1000 Bus Matrix BF88_2000 DMA BF88_3000 Prefetch Cache BF88_4000 GPIO BF88_6000 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Virtual Address End BF80_01FF BF80_03FF BF80_07FF BF80_09FF BF80_0BFF BF80_0DFF BF80_0FFF BF80_21FF BF80_23FF BF80_25FF BF80_27FF BF80_29FF BF80_31FF ...
Page 114
... PIC32MX3XX/4XX NOTES: DS61143C-page 112 Preliminary © 2008 Microchip Technology Inc. ...
Page 115
... RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG meth- ods are described in the “PIC32MX3XX/4XX Program- ming Specification” (DS61145) document, which may be downloaded from the Microchip web site. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 113 ...
Page 116
... FCEIP<2:0> Preliminary Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 — — — — — — — — — NVMOP<3:0> Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 — USBIE FCEIE — USBIF FCEIF FCEIS<1:0> © 2008 Microchip Technology Inc. ...
Page 117
... This bit is read-only and is automatically set by hardware 1 = Low-voltage event active 0 = Low-voltage event NOT active Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). bit 10-4 Reserved: Maintain as ‘0’; ignore read © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — ...
Page 118
... Page erase operation: erases page selected by NVMADDR not write-protected 0011 = Row program operation: programs row selected by NVMADDR not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADD not write-protected 0000 = No operation DS61143C-page 116 Preliminary © 2008 Microchip Technology Inc. ...
Page 119
... The CPU will not execute any instruc- tion, or respond to interrupts, during this time. If any interrupts occur during the programming cycle, they remain pending until the cycle completes. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 7.3 Control Registers There are two SFRs used to erase and write the PFM: NVMCON and NVMKEY ...
Page 120
... For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. Preliminary © 2008 Microchip Technology Inc. in NVMADDR and ...
Page 121
... Set NVMADDR to Start Address of row to program NVMADDR = (unsigned int) address; // Set NVMSRCADDR to the SRAM data buffer Address NVMSRCADDR = (unsigned int) data; // Unlock and Write Row res = NVMUnlock(0x4003); // Return Result return res; } © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 119 ...
Page 122
... NVMWriteWord (void* address, unsigned int data) { unsigned int res; // Load data into NVMDATA register NVMDATA = data; // Load address to program into NVMADDR register NVMADDR = (unsigned int) address; // Unlock and Write Word res = NVMUnlock (0x4001); // Return Result return res; } DS61143C-page 120 Preliminary © 2008 Microchip Technology Inc. ...
Page 123
... Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } unsigned int NVMErasePFM(void) { unsigned int res; // Unlock and Erase Program Flash res = NVMUnlock(0x4005); // Return Result return res; } © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 121 ...
Page 124
... PIC32MX3XX/4XX NOTES: DS61143C-page 122 Preliminary © 2008 Microchip Technology Inc. ...
Page 125
... For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX3XX/4XX interrupts module includes the following features: • ...
Page 126
... Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 — — — — — SS0 TPC<2:0> INT2EP INT1EP INT0EP — — — — — — RIPL<2:0> VEC<5:0> U1EIF SPI1RXIF SPI1TXIF OC4IF IC4IF T4IF OC2IF IC2IF T2IF CS1IF CS0IF CTIF © 2008 Microchip Technology Inc. ...
Page 127
... IPC2 31:24 — 23:16 — 15:8 — 7:0 — BF88_10B4 IPC2CLR 31:0 BF88_10B8 IPC2SET 31:0 BF88_10BC IPC2INV 31:0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 — — — — — — — DMA3IF FSCMIF ...
Page 128
... Write inverts the selected bits in IPC8, read yields undefined value Preliminary Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 INT3IS<1:0> OC3IS<1:0> IC3IS<1:0> T3IS<1:0> INT4IS<1:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> SPI1IS<1:0> OC5IS<1:0> IC5IS<1:0> T5IS<1:0> AD1IS<1:0> CNIS<1:0> I2C1IS<1:0> U1IS<1:0> SPI2IS<1:0> CMP2IS<1:0> CMP1IS<1:0> PMPIS<1:0> RTCCIS<1:0> FSCMIS<1:0> I2C2IS<1:0> U2IS<1:0> © 2008 Microchip Technology Inc. ...
Page 129
... IPC11 31:24 — 23:16 — 15:8 — 7:0 — BF88_1144 IPC11CLR 31:0 BF88_1148 IPC11SET 31:0 BF88_114C IPC11INV 31:0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 — — DMA3IP<2:0> — — DMA2IP<2:0> — — DMA1IP<2:0> ...
Page 130
... R/W-0 r-x R/W-0 MVEC — R/W-0 R/W-0 R/W-0 INT4EP INT3EP INT2EP P = Programmable bit Preliminary r-x r-x — — bit 24 r-x R/W-0 — SS0 bit 16 R/W-0 R/W-0 TPC<2:0> bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 131
... INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 129 ...
Page 132
... R-0 — — R-0 R-0 R-0 VEC<5:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. r-x r-x — — bit 24 r-x r-x — — bit 16 R-0 R-0 RIPL<2:0> bit 8 R-0 R-0 bit 0 ...
Page 133
... Bit value at POR (‘0’, ‘1’ Unknown) bit 31-0 IPTMR: Interrupt Proximity Timer Reload bits Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an interrupt event. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-0 R/W-0 R/W-0 IPTMR< ...
Page 134
... R/W-0 R/W-0 T3IF INT2IF OC2IF R/W-0 R/W-0 R/W-0 T1IF INT0IF CS1IF P = Programmable bit Preliminary R/W-0 R/W-0 SPI1RXIF SPI1TXIF bit 24 R/W-0 R/W-0 IC4IF T4IF bit 16 R/W-0 R/W-0 IC2IF T2IF bit 8 R/W-0 R/W-0 CS0IF CTIF bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 135
... No interrupt request has a occurred bit 7 INT1IF: External Interrupt 1 Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred bit 6 OC1IF: Output Compare 1 Interrupt Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 133 ...
Page 136
... No interrupt request has a occurred bit 1 CS0IF: Core Software Interrupt 0 Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred bit 0 CTIF: Core Timer Interrupt Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred DS61143C-page 134 Preliminary © 2008 Microchip Technology Inc. ...
Page 137
... RTCCIF: Real Time Clock Interrupt Flag bit 1 = Interrupt request has occurred interrupt request has a occurred bit 14 FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit 1 = Interrupt request has occurred interrupt request has a occurred © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — — ...
Page 138
... No interrupt request has a occurred bit 1 AD1IF: Analog-to-Digital 1 Interrupt Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred bit 0 CNIF: Input Change Interrupt Request Flag bit 1 = Interrupt request has occurred interrupt request has a occurred DS61143C-page 136 Preliminary © 2008 Microchip Technology Inc. ...
Page 139
... Interrupt is enabled 0 = Interrupt is disabled bit 24 SPI1TXIE: SPI1 Transmitter Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 23 SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE U1EIE R/W-0 R/W-0 R/W-0 ...
Page 140
... Interrupt is disabled bit 8 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 7 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 OC1IE: Output Compare 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS61143C-page 138 Preliminary © 2008 Microchip Technology Inc. ...
Page 141
... CS1IE: Core Software Interrupt 1 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 CS0IE: Core Software Interrupt 0 Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 CTIE: Core Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 139 ...
Page 142
... R/W-0 R/W-0 I2C2SIE I2C2BIE U2TXIE R/W-0 R/W-0 R/W-0 CMP2IE CMP1IE PMPIE P = Programmable bit Preliminary r-x R/W-0 USBIE FCEIE bit 24 R/W-0 R/W-0 DMA1IE DMA0IE bit 16 R/W-0 R/W-0 U2RXIE U2EIE bit 8 R/W-0 R/W-0 AD1IE CNIE bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 143
... PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 AD1IE: Analog-to-Digital 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 CNIE: Input Change Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 141 ...
Page 144
... R/W-0 R/W-0 INT0IP<2:0> R/W-0 R/W-0 R/W-0 CS1IP<2:0> R/W-0 R/W-0 R/W-0 CS0IP<2:0> R/W-0 R/W-0 R/W-0 CTIP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 INT0IS<1:0> bit 24 R/W-0 R/W-0 CS1IS<1:0> bit 16 R/W-0 R/W-0 CS0IS<1:0> bit 8 R/W-0 R/W-0 CTIS<1:0> bit Reserved bit ...
Page 145
... Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 CTIS<1:0>: Core Timer Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 143 ...
Page 146
... R/W-0 R/W-0 INT1IP<2:0> R/W-0 R/W-0 R/W-0 OC1IP<2:0> R/W-0 R/W-0 R/W-0 IC1IP<2:0> R/W-0 R/W-0 R/W-0 T1IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 INT1IS<1:0> bit 24 R/W-0 R/W-0 OC1IS<1:0> bit 16 R/W-0 R/W-0 IC1IS<1:0> bit 8 R/W-0 R/W-0 T1IS<1:0> bit Reserved bit ...
Page 147
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 T1IS<1:0>: Timer1 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 145 ...
Page 148
... R/W-0 R/W-0 INT2IP<2:0> R/W-0 R/W-0 R/W-0 OC2IP<2:0> R/W-0 R/W-0 R/W-0 IC2IP<2:0> R/W-0 R/W-0 R/W-0 T2IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 INT2IS<1:0> bit 24 R/W-0 R/W-0 OC2IS<1:0> bit 16 R/W-0 R/W-0 IC2IS<1:0> bit 8 R/W-0 R/W-0 T2IS<1:0> bit Reserved bit ...
Page 149
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 T2IS<1:0>: Timer2 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 147 ...
Page 150
... R/W-0 R/W-0 INT3IP<2:0> R/W-0 R/W-0 R/W-0 OC3IP<2:0> R/W-0 R/W-0 R/W-0 IC3IP<2:0> R/W-0 R/W-0 R/W-0 T3IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 INT3IS<1:0> bit 24 R/W-0 R/W-0 OC3IS<1:0> bit 16 R/W-0 R/W-0 IC3IS<1:0> bit 8 R/W-0 R/W-0 T3IS<1:0> bit Reserved bit ...
Page 151
... Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T3IS<1:0>: Timer3 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 149 ...
Page 152
... INT4IP<2:0> R/W-0 R/W-0 R/W-0 OC4IP<2:0> R/W-0 R/W-0 R/W-0 IC4IP<2:0> R/W-0 R/W-0 R/W-0 T4IP<2:0> R/W-0 R/W-0 R/W Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 INT4IS<1:0> bit 24 R/W-0 R/W-0 OC4IS<1:0> bit 16 R/W-0 R/W-0 IC4IS<1:0> bit 8 R/W-0 R/W-0 T4IS<1:0> R/W-0 R/W-0 ...
Page 153
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 T4IS<1:0>: Timer4 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 151 ...
Page 154
... R/W-0 R/W-0 SPI1IP<2:0> R/W-0 R/W-0 R/W-0 OC5IP<2:0> R/W-0 R/W-0 R/W-0 IC5IP<2:0> R/W-0 R/W-0 R/W-0 T5IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 SPI1IS<1:0> bit 24 R/W-0 R/W-0 OC5IS<1:0> bit 16 R/W-0 R/W-0 IC5IS<1:0> bit 8 R/W-0 R/W-0 T5IS<1:0> bit Reserved bit ...
Page 155
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 T5IS<1:0>: Timer5 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 153 ...
Page 156
... Reserved: Maintain as ‘0’; ignore read DS61143C-page 154 R/W-0 R/W-0 R/W-0 AD1IP<2:0> R/W-0 R/W-0 R/W-0 CNIP<2:0> R/W-0 R/W-0 R/W-0 I2C1IP<2:0> R/W-0 R/W-0 R/W-0 U1IP<2:0> Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 AD1IS<1:0> bit 24 R/W-0 R/W-0 CNIS<1:0> bit 16 R/W-0 R/W-0 I2C1IS<1:0> bit 8 R/W-0 R/W-0 U1IS<1:0> bit 0 ...
Page 157
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 U1IS<1:0>: UART1 Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 155 ...
Page 158
... R/W-0 R/W-0 SPI2IP<2:0> R/W-0 R/W-0 R/W-0 CMP2IP<2:0> R/W-0 R/W-0 R/W-0 CMP1IP<2:0> R/W-0 R/W-0 R/W-0 PMPIP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 SPI2IS<1:0> bit 24 R/W-0 R/W-0 CMP2IS<1:0> bit 16 R/W-0 R/W-0 CMP1IS<1:0> bit 8 R/W-0 R/W-0 PMPIS<1:0> bit Reserved bit ...
Page 159
... Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 PMPIS<1:0>: Parallel Master Port Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 157 ...
Page 160
... R/W-0 R/W-0 RTCCIP<2:0> R/W-0 R/W-0 R/W-0 FSCMIP<2:0> R/W-0 R/W-0 R/W-0 I2C2IP<2:0> R/W-0 R/W-0 R/W-0 U2IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 RTCCIS<1:0> bit 24 R/W-0 R/W-0 FSCMIS<1:0> bit 16 R/W-0 R/W-0 I2C2IS<1:0> bit 8 R/W-0 R/W-0 U2IS<1:0> bit Reserved bit ...
Page 161
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 U2IS<1:0>: UART2 subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 159 ...
Page 162
... R/W-0 R/W-0 DMA3IP<2:0> R/W-0 R/W-0 R/W-0 DMA2IP<2:0> R/W-0 R/W-0 R/W-0 DMA1IP<2:0> R/W-0 R/W-0 R/W-0 DMA0IP<2:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 DMA3IS<1:0> bit 24 R/W-0 R/W-0 DMA2IS<1:0> bit 16 R/W-0 R/W-0 DMA1IS<1:0> bit 8 R/W-0 R/W-0 DMA0IS<1:0> bit Reserved bit ...
Page 163
... Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 DMA0IS<1:0>: DMA0 Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 161 ...
Page 164
... P = Programmable bit Preliminary © 2008 Microchip Technology Inc. r-x r-x — — bit 24 r-x r-x — — bit 16 r-x r-x — — bit 8 r-x r-x — ...
Page 165
... Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 FCEIS<1:0>: Flash Control Event Interrupt Subpriority bits 11 = Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority is 0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — — — r-x ...
Page 166
... Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge Synchronous Edge w/Idle Synchronous Edge Synchronous Level Edge Synchronous Edge w/Idle Level Level © 2008 Microchip Technology Inc. ...
Page 167
... DMA3 – DMA Channel 3 FCE – Flash Control Event USB (Reserved) Note 1: The “IRQ Number” in Table 8-2 is also the “Interrupt Number” listed in the IFSx, IECx and IPSx register definitions. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Vector (1) IRQ Number 37 31 ...
Page 168
... Changing interrupt controller modes after initialization may result in undefined behavior. The M4K core supports several different interrupt processing modes. The interrupt controller is designed to work in External Interrupt Controller mode. Preliminary © 2008 Microchip Technology Inc. ...
Page 169
... FIGURE 8-2: INTERRUPT PROCESS ENCODE Vector Number Requested IPL Shadow Set Number Note: SRSCtl, Cause, Status, and IntCtl registers are CPU registers and are described in Section 2. “CPU”. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX LATCH COMPARE GENERATE Any Request RIPL > ...
Page 170
... Get Status // Set BEV bit // Update Status // Set an EBase value of 0xBD000000 // Set the Vector Spacing to non-zero value // Get Cause // Set IV // Update Cause // Get Status // Clear BEV and EXL // Update Status // Clear MVEC bit // Enable all interrupts Preliminary © 2008 Microchip Technology Inc. ...
Page 171
... INTCONSET = 0x1000; asm(“ie”); © 2008 Microchip Technology Inc. PIC32MX3XX/4XX To configure the CPU in Multi-Vector mode, the follow- ing CPU registers (IntCtl, Cause, and Status) and the INTCON register must be configured as follows: • EBase ≠ 00000 • ...
Page 172
... These bits define the subpriority within the priority level of the vector. The user- selectable subpriority levels range from 0 (the lowest subpriority (the highest). Multi-Vector initialization // clear the subpriority level // set the subpriority to 2 Preliminary © 2008 Microchip Technology Inc. ...
Page 173
... Status<2>) are cleared and the Master Interrupt Enable bit (Status<0>) is set. Finally, the General Purpose Registers will be saved on the stack. (The Cause and Status registers are located in the CPU.) © 2008 Microchip Technology Inc. PIC32MX3XX/4XX EXAMPLE 8-5: SINGLE VECTOR INTERRUPT HANDLER ...
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... Preliminary © 2008 Microchip Technology Inc. Priority bits, RIPLx ...
Page 175
... EPC lw k0, 4(sp) mtc0 k0, Status eret © 2008 Microchip Technology Inc. PIC32MX3XX/4XX EXAMPLE 8-10: EPILOGUE WITH A DEDICATED GENERAL PURPOSE REGISTER SET IN ASSEMBLY CODE // end of interrupt handler code addu sp, s8, zero di lw k0, 0(sp) mtc0 k0, EPC ...
Page 176
... IEC0CLR = 0x00008000; INTCONCLR = 0x00000008; IFS0CLR = 0x00008000; IEC0SET = 0x00008000; DS61143C-page 174 // disable INT3 // clear the bit for falling edge trigger // clear the interrupt flag // enable INT3 Preliminary © 2008 Microchip Technology Inc. ...
Page 177
... INTCONCLR = 0x00000700; IPTMPCLR = 0xFFFFFFFF; INTCONSET = 0x00000300; IPTMR = 0x12345678; © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Interrupt proximity interrupt uses the interrupt proximity timer, IPTMR, to create a temporal window in which a group of interrupts of the same, or lower, priority will be held off. The user can activate temporal proximity inter- rupt coalescing by performing the following steps: • ...
Page 178
... PIC32MX3XX/4XX NOTES: DS61143C-page 176 Preliminary © 2008 Microchip Technology Inc. ...
Page 179
... Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Pre-Fetch Tag © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 9.1 Features • 16 Fully Associative Lockable Cache Lines • 16-byte Cache Lines • Cache Lines allocated to Data • 2 Cache Lines with Address Mask to hold repeated instructions • ...
Page 180
... CHECOH — DCSZ<1:0> PFMWS<2:0> — — — — — — — — — CHEIDX<3:0> — — — LLOCK LTYPE — — — — — — — — — — — — CHELRU<24> © 2008 Microchip Technology Inc. ...
Page 181
... PREFETCH SFR SUMMARY (CONTINUED) Virtual Bit Name Address 31/23/15/7 BF88_40A0 CHEMIS 31:24 23:16 15:8 7:0 BF88_40C0 CHEPFABT 31:24 23:16 15:8 7:0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 CHEMIS<31:24> CHEMIS<23:16> CHEMIS<15:8> CHEMIS<7:0> CHEPFABT<31:24> CHEPFABT<23:16> ...
Page 182
... R/W-0 r-x R/W-1 — Programmable bit Preliminary © 2008 Microchip Technology Inc. r-x r-x — — bit 24 r-x R/W-0 — CHECOH bit 16 R/W-0 R/W-0 DCSZ<1:0> bit 8 R/W-1 R/W-1 PFMWS<2:0> ...
Page 183
... Seven Wait states 110 = Six Wait states 101 = Five Wait state 100 = Four Wait states 011 = Three Wait states 010 = Two Wait states 001 = One Wait state 000 = Zero Wait states © 2008 Microchip Technology Inc. PIC32MX3XX/4XX Preliminary DS61143C-page 181 ...
Page 184
... R/W-0 R/W-0 — CHEIDX<3:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. r-x r-x — — bit 24 r-x r-x — — bit 16 r-x r-x — — bit 8 R/W-0 R/W-0 ...
Page 185
... The line is not locked and can be replaced bit 1 LTYPE: Line Type bit 1 = The line caches instruction words 0 = The line caches data words bit 0 Reserved: Note 1: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>). © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — — — ...
Page 186
... R/W-0 R/W-0 R/W-0 LMASK<15:8> r-x r-x r-x — — — Programmable bit Preliminary © 2008 Microchip Technology Inc. r-x r-x — — bit 24 r-x r-x — — bit 16 R/W-0 R/W-0 bit 8 r-x r-x — — ...
Page 187
... R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-x R/W-x R/W-x CHEW0<31:24> R/W-x ...
Page 188
... Readable only if the device is not code-protected. DS61143C-page 186 R/W-x R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x R/W-x CHEW1<23:16> R/W-x R/W-x R/W-x CHEW1<15:8> R/W-x R/W-x R/W-x CHEW1<7:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-x R/W-x bit 24 R/W-x R/W-x bit 16 R/W-x R/W-x bit 8 R/W-x R/W-x bit Reserved bit ...
Page 189
... R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-x R/W-x R/W-x CHEW2<31:24> R/W-x ...
Page 190
... This register is a window into the cache data array and is readable only if the device is not code-protected. DS61143C-page 188 R/W-x R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x R/W-x CHEW3<23:16> R/W-x R/W-x R/W-x CHEW3<15:8> R/W-x R/W-x R/W-x CHEW3<7:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-x R/W-x bit 24 R/W-x R/W-x bit 16 R/W-x R/W-x bit 8 R/W-x R/W-x bit Reserved bit ...
Page 191
... Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-25 Reserved: Maintain as ‘0’; ignore read bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits CHELRU indicates the Pseudo-LRU state of the cache. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX r-x r-x r-x — ...
Page 192
... Non-cacheable accesses do not modify this value. DS61143C-page 190 R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x R/W-x CHEHIT<23:16> R/W-x R/W-x R/W-x CHEHIT<15:8> R/W-x R/W-x R/W-x CHEHIT<7:0> Programmable bit Preliminary © 2008 Microchip Technology Inc. R/W-x R/W-x bit 24 R/W-x R/W-x bit 16 R/W-x R/W-x bit 8 R/W-x R/W-x bit Reserved bit ...
Page 193
... Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-0 CHEMIS<31:0>: Cache Miss Count bits Incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. Non-cacheable accesses do not modify this value. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX R/W-x R/W-x R/W-x CHEMIS< ...
Page 194
... DS61143C-page 192 R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x R/W-x PFABT<15:8> CHE R/W-x R/W-x R/W-x CHEPFABT<7:0> Programmable bit Preliminary R/W-x R/W-x bit 24 R/W-x R/W-x bit 16 R/W-x R/W-x bit 8 R/W-x R/W-x bit Reserved bit © 2008 Microchip Technology Inc. ...
Page 195
... EXAMPLE 9-2: EXAMPLE CODE: LOCKING A LINE IN PREFETCH MODULE #define LOCKED_LINE_NUM 3 /* lock first line of func1() in cache */ CHEACC = (1<<31) | LOCKED_LINE_NUM; tmp = (unsigned long)func1; ltagboot = (tmp & 0x00c00000 CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0 © 2008 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 9-2: DCSZ<1:0> The CHECON ...
Page 196
... Setting up the address mask such that more than one line will match an address causes undefined results. Therefore highly recommended to set up masking before entering cacheable code. // locked and invalid Preliminary © 2008 Microchip Technology Inc. ...
Page 197
... The predictive prefetch does not resume, but instead waits for another instruction fetch. At which time, it either fills the buffer because of a miss, or starts a prefetch because of a hit. © 2008 Microchip Technology Inc. PIC32MX3XX/4XX 9.3.5 COHERENCY SUPPORT It is not possible to execute out of cache while pro- gramming the flash memory ...
Page 198
... PIC32MX3XX/4XX NOTES: DS61143C-page 196 Preliminary © 2008 Microchip Technology Inc. ...
Page 199
... Channel-to-channel chaining TABLE 10-1: DMA CONTROLLER FEATURES <= 256B Yes Yes © 2008 Microchip Technology Inc. PIC32MX3XX/4XX • Flexible DMA Requests DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request ...
Page 200
... DMAADDR<23:16> DMAADDR<15:8> DMAADDR<7:0> Preliminary Device Bus + Bus Arbitration Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 — — — — — — — — — — — — — — — — — — — — — DMACH<1:0> © 2008 Microchip Technology Inc. ...