PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 400

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
17.3
The SPI module has the ability to generate interrupts
reflecting the events that occur during the data commu-
nication. The following types of interrupts can be
generated:
• Receive data available interrupts, signalled by
• Transmit buffer empty interrupts, signalled by
• Receive buffer overflow interrupts, signalled by
EXAMPLE 17-3:
DS61143C-page 398
/*
*/
SPI1RXIF (IFS0<25>), SPI2RXIF (IFS1<7>). This
event occurs when there is new data assembled
in the SPIxBUF receive buffer.
SPI1TXIF (IFS0<24>), SPI2TXIF (IFS1<6>). This
event occurs when there is space available in the
SPIxBUF transmit buffer and new data can be
written.
SPI1EIF (IFS0<23>), SPI2EIF(IFS1<5>).
This event occurs when there is an overflow
condition for the SPIxBUF receive buffer, i.e., new
receive data assembled but the previous one is
not read.
The following code example illustrates an SPI1 interrupt configuration.
When the SPI1 interrupt is generated, the cpu will jump to the vector assigned to SPI1
interrupt.
It assumes that none of the SPI1 input pins are shared with an analog input.
If so, the AD1PCFG and corresponding TRIS registers have to be properly configured.
int rData;
IEC0CLR=0x03800000;
SPI1CON = 0;
rData=SPI1BUF;
IFS0CLR=0x03800000;
IPC5CLR=0x1f000000;
IPC5SET=0x0d000000;
IEC0SET=0x03800000;
SPI1BRG=0x1;
SPI1STATCLR=0x40;
SPI1CON=0x8220;
SPI Interrupts
SPI INITIALIZATION WITH INTERRUPTS ENABLED
// disable all SPI interrupts
// Stops and resets the SPI1.
// clears the receive buffer
// clear any existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable Rx, Tx and Error interrupts
// use F
// clear the Overflow
// SPI ON, 8 bits transfer, SMP=1, Master Mode
Preliminary
PB
/4 clock frequency
An SPI device is enabled as a source of interrupts via
the respective SPI interrupt enable bits:
• SPI1RXIE (IEC0<25>) and SPI2RXIE (IEC1<7>)
• SPI1TXIE (IEC0<24>) and SPI2TXIE (IEC1<6>)
• SPI1EIE (IEC0<23>) and SPI2EIE (IEC1<5>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• SPI1IP (IPC5<28:26>), SPI1IS (IPC5<25:24>)
• SPI2IP (IPC7<28:26>), SPI2IS (IPC7<25:24>)
In addition to enabling the SPI interrupts, an Interrupt
Service Routine, ISR, is required. Example 17-3 is a
partial code example of an ISR.
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
© 2008 Microchip Technology Inc.