PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 385

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.2.2
In Master mode, data from the SPIxBUF register is
transmitted synchronously on the SDO (output) pin
while synchronous data is received from the slave
device on the SDI (input) pin. In this mode, the Master
controls the synchronous data transfer with the SCK
clock pin by generating 8, 16 or 32 clock pulses,
depending on the selected data size.
17.2.2.1
In Master mode the SCK and SDO pins are outputs and
the SDI pin is an input. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired. Refer to
Table 17-7.
The SDI (input) must be configured to properly sample
the data received from the slave device by configuring
the sample bit, SMP (SPIxCON<9>).
In Master mode, the SCK clock edge and polarity must
be configured properly for the master and slave device
to correctly transfer data synchronously. Refer to the
timing diagram shown in Figure 17-3 to determine the
appropriate settings.
In Master mode, the data transfers can be 8, 16, or 32
bits
MODE<32,16> (SPIxCON<11:10>). Refer to Section
17.2.1 “8, 16, 32-Bit Operation”.
In Master mode, the system clock is divided and then
used as the serial clock. The division is based on the
settings
Section 17.2.5 “SPI Master Mode Clock Fre-
quency”.
17.2.2.2
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode
• Disable Framed SPI support
The
configurations and may be configured as desired:
• Enable module control of SDO pin – DISSDO
• Configure SCK clock polarity to idle high –
• Configure SCK clock edge transition from Idle to
• Select 16-bit data width –
• Sample data input at middle –
• Enable SPI module when CPU idle –
© 2008 Microchip Technology Inc.
FRMEN (SPIxCON<31>) = 0
(SPIxCON<12>) = 0
active – CKE (SPIxCON<8>) = 0
MSTEN (SPIxCON<5>) = 1.
CKP (SPIxCON<6>) = 1
MODE<32,16> (SPIxCON<11:10>) = 01
SMP (SPIxCON<9>) = 0
SIDL (SPIxCON<13>) = 0
and
remaining
in
MASTER MODE
are
Master Mode Operations
Master SPIxCON Configuration
the
configured
bits
SPIxBRG
are
shown
using
register.
with
control
Refer
example
bits,
Preliminary
to
17.2.2.3
The following steps should be performed to setup the
SPI module for the Master mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note 1: When using the Slave Select mode, the
If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
Stop and reset the SPI module by clearing the
ON bit.
Clear the receive buffer.
If interrupts are used, the following additional
steps are performed:
• Clear the SPIx interrupt flags/events in the
• Set the SPIx interrupt enable bits in the
• Write the SPIx interrupt priority and subprior-
Write the Baud Rate register, SPIxBRG.
Clear the SPIROV bit (SPIxSTAT<6>).
Write the selected configuration settings to the
SPIxCON register.
Enable SPI operation by setting the ON bit
(SPIxCON<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
respective IFS0/1 register.
respective IEC0/1 register.
ity bits in the respective IPC5/7 register.
PIC32MX3XX/4XX
2: The user must turn off the SPI device
3: The SPI device must be turned off prior to
4: The SPIxSR register cannot be written to
SSx or another GPIO pin is used to con-
trol the slave’s SSx input. The pin must
be controlled in software.
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
changing the mode from Slave to Master.
directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
Master Mode Initialization
DS61143C-page 383