PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 452

IC PIC MCU FLASH 512K 100-TQFP

PIC32MX460F512L-80I/PT

Manufacturer Part Number
PIC32MX460F512L-80I/PT
Description
IC PIC MCU FLASH 512K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX460F512L-80I/PT
Manufacturer:
VISHAY
Quantity:
3 200
Part Number:
PIC32MX460F512L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX460F512L-80I/PT
0
PIC32MX3XX/4XX
20.3.2
The Master mode initialization properly prepares the
PMP port for communicating with an external device.
The following steps should be performed to properly
configure the PMP port:
1.
2.
3.
EXAMPLE 20-1:
20.3.3
To perform a read on the parallel bus, the user reads
the PMDIN register. The effect of reading the PMDIN
register retrieves the current value and causes the
PMP to activate the Chip Select lines and the address
bus. The read line PMRD is strobed and the new data
is latched into the PMDIN register, making it available
for the next time the PMDIN register is read.
DS61143C -page 450
IEC1CLR = 0x0004;
PMCON = 0x0BC0;
PMMODE = 0x2A04;
PMAEN = 0xFF00;
IPC7SET = 0x001C;
IPC7SET = 0x0003;
IFS1CLR
IEC1SET
PMCONSET = 0x8000;
PMADDR = 0x4000;
PMDIN = 0x1234;
...
If interrupts are used, disable the PMP interrupt
by clearing the interrupt enable bit PMPIE
(IEC1<2>) = 0.
Stop and reset the PMP module by clearing the
control bit ON (PMCON<15>) = 0.
Configure the desired settings in the PMCON,
PMMODE and PMAEN control registers.
MASTER PORT INITIALIZATION
READ OPERATION
= 0x0004;
= 0x0004;
PARALLEL MASTER PORT INITIALIZATION
//Disable PMP int
//Stop and Configure
//Config PMMODE reg
//Config PMAEN reg
//Priority level=7
//subpriority=3
//Same as..
//IPC7SET=0x001F
//Clear PMP flag
//Enable PMP int
//Enable PMP
//Set external address
//Write to device
Preliminary
4.
5.
Refer to the PIC32MX3XX/4XX Reference Manual for
a detailed description of the read operation and illus-
trated example.
Note:
If interrupts are used:
a)
b)
c)
Enable the PMP master port by setting control
bit ON = 1.
Clear interrupt flag bit PMPIF
(IFS1<2>) = 0.
Configure the PMP interrupt priority bits
PMPIP<2:0> (IPC7<4:2>) and interrupt sub
priority bits PMPIS (IPC7<1:0>.
Enable PMP interrupt by setting interrupt
enable bit PMPIE = 1.
The read data obtained from the PMDIN
register is actually the read value from the
previous read operation. Hence, the first
user read will be a dummy read to initiate
the first bus read and fill the read register.
Also, the requested read value will not be
ready until after the BUSY bit is observed
low. Therefore, in a back-to-back read
operation, the data read from the register
will be the same for both reads. The next
read of the register will yield the new
value.
© 2008 Microchip Technology Inc.

Related parts for PIC32MX460F512L-80I/PT