PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 467

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 21-2:
© 2008 Microchip Technology Inc.
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31-16
bit 15
bit 14
bit 13
bit 12
ALRMEN
R/W-0
R/W-0
r-x
r-x
—
—
Reserved: Maintain as ‘0’; ignore read
ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
Note: Hardware clears ALRMEN anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME: Chime Enable bit
1 = Chime is enabled – ARPT<7:0> is allowed to roll over from 00 to FF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 00
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
PIV: Alarm Pulse Initial Value bit
When ALRMEN = 0, PIV is writable and determines the initial value of the alarm pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the alarm pulse.
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half-second rollover during a read.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because prescaler is
Note: This assumes a CPU read will execute in less than 32 PBCLKs.
CHIME
R/W-0
R/W-0
The ARPT must be read repeatedly until the same value is read twice. This must be done since
multiple bits may be changing, which are then synchronized to the PB clock domain.
> 32 RTC clock away from a half-second rollover
r-x
r-x
—
—
RTCALRM: RTC ALARM CONTROL REGISTER
CHIME = 0. This field should not be written when RTCCON = 1 (RTCCON<15>) and
ALRMSYNC = 1.
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
R/W-0
R/W-0
PIV
r-x
r-x
—
—
ALRMSYNC
R/W-0
Preliminary
R-0
r-x
r-x
—
—
ARPT<7:0>
P = Programmable bit
R/W-0
R/W-0
r-x
r-x
—
—
PIC32MX3XX/4XX
(1)
R/W-0
R/W-0
r-x
r-x
—
—
AMASK<3:0>
r = Reserved bit
R/W-0
R/W-0
r-x
r-x
—
—
DS61143C-page 465
R/W-0
R/W-0
r-x
r-x
—
—
bit 24
bit 16
bit 8
bit 0