PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 172

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
8.5
8.5.1
The user is able to assign a group priority to each of the
interrupt vectors. The groups’ priority level bits are
located in the IPCx register. Each IPCx register con-
tains group priority bits for four interrupt vectors. The
user-selectable priority levels range from 1 (the lowest
priority) to 7 (the highest). If an interrupt priority is set to
zero, the interrupt vector is disabled for both interrupt
and wake-up purposes. Interrupt vectors with a higher
priority level preempt lower priority interrupts. The user
must move the Requested Interrupt Priority bit of the
EXAMPLE 8-3:
8.5.2
The user can assign a subpriority level within each
group priority. The subpriority will not cause preemption
of an interrupt in the same priority; rather, if two inter-
rupts with the same priority are pending, the interrupt
with the highest subpriority will be handled first. The
subpriority bits are located in the IPCx register. Each
EXAMPLE 8-4:
DS61143C-page 170
/*
The following code example will set the subpriority to level 2.
must be performed (See Example 8-2)
*/
IPC0CLR = 0x00000003;
IPC0SET = 0x00000002;
/*
The following code example will set the priority to level 2.
must be performed (See Example 8-2)
*/
IPC0CLR = 0x0000001C;
IPC0SET = 0x00000008;
Interrupt Priorities
INTERRUPT GROUP PRIORITY
INTERRUPT SUBPRIORITY
SETTING GROUP PRIORITY LEVEL
SETTING SUBPRIORITY LEVEL
// clear the subpriority level
// set the subpriority to 2
// clear the priority level
// set priority level to 2
Preliminary
Cause register, RIPLx (Cause<15:10>), into the Status
register’s Interrupt Priority bits, IPLx (Status<15:10>),
before re-enabling interrupts. (The Cause and Status
registers are located in the CPU; refer to Section 2.0
"PIC32MX MCU" of this manual for more information.)
This action will disable all lower priority interrupts until
the completion of the Interrupt Service Routine.
IPCx register contains subpriority bits for four of the
interrupt vectors. These bits define the subpriority
within the priority level of the vector. The user-
selectable subpriority levels range from 0 (the lowest
subpriority) to 3 (the highest).
Note:
The Interrupt Service Routine (ISR) must
clear the associated interrupt flag in the
IFSx register before lowering the interrupt
priority level to avoid recursive interrupts.
Multi-Vector initialization
Multi-Vector initialization
© 2008 Microchip Technology Inc.